🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

AMBA AXI VIP

Code generation tool for control and status registers

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

Network on Chip Implementation written in SytemVerilog

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Control and status register code generator toolchain

OPAE porting to Xilinx FPGA devices.

Simple single-port AXI memory interface

An open-source HDL register code generator fast enough to run in real time.

Xilinx PCIe to MIG DDR4 example designs and custom part data files

Xilinx AXI VIP example of use

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

Implementation of the Advanced Encryption Standard in Chisel

AXI X-Bar

XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA

VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.