Build software better, together

suoto / hdl_checker

Repurposing existing HDL tools to help writing better code

Updated Sep 23, 2026
Python

Arjun-Narula / Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

traffic verilog vivado verilog-hdl traffic-light traffic-sign-recognition vivado-hls verilog-programs verilog-simulator verilog-project verilog-code vivado-simulator

Updated Jul 18, 2020
JavaScript

wyvernSemi / mem_model

Star

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

simulation vhdl verilog questasim ghdl avalon memory-model test-bench pli verilog-components verilator axi nvc dpi-c cosimulation vivado-simulator verilog-testbenches

Updated Feb 2, 2026
VHDL

arhamhashmi01 / Axi4-lite

Star

This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.

systemverilog hardware-designs verilator axi4-lite axi4-protocol vivado-simulator axi4-lite-interface

Updated May 4, 2024
SystemVerilog

esynr3z / pyhdlsim

Star

Example of Python and PyTest powered workflow for a HDL simulation

python asic fpga pytest rtl verilog icarus-verilog hdl modelsim system-verilog vivado-simulator

Updated Jan 17, 2021
Python

Ross0907 / Vivado-WDB-Waveform-Converter

Star

Convert Vivado/VCD/XSim WDB and WCFG waveform databases directly to VCD, CSV, JSON and Excel. GUI, batch conversion, signal filtering and radix controlls.

python fpga amd vhdl waveform python-script verilog vivado systemverilog vcd wdb tcl-scripts xsim vivado-simulator wcfg waveform-converter

Updated Sep 14, 2026
Python

mzh330521 / SublimeLinter-contrib-xsim

Star

Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL.

sublime-text vhdl sublimelinter linter-plugin verilog systemverilog xsim vivado-simulator

Updated May 29, 2024
Python

RipperJ / VerilogExpr2NAND-NOR

Star

Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation

compiler simulation lex espresso ply verilog yacc boolean-expression nand logic-minimization nor xsim vivado-simulator pyeda

Updated Jun 4, 2023
Python

Ammar-Bin-Amir / SystemVerilog_Practice

Star

Practice Codes of SystemVerilog Language

vscode systemverilog vivado-simulator

Updated May 19, 2024
SystemVerilog

VRM21-Studios / VRM21-NPU-Series

Star

A collection of FPGA-oriented AI accelerator RTL designs, including an 8x8 weight-stationary systolic array and a parameterized event-driven SNN/LIF accelerator, targeting the AMD Kria KV260.

fpga verilog xilinx spiking-neural-networks vivado systemverilog fixed-point verilog-hdl snn axi-stream systemverilog-simulation vivado-simulator axi-lite systemverilog-test-bench systolic-array kria-kv260

Updated Sep 6, 2026
SystemVerilog

Raveem13 / axi-matrix-accelerator

Star

This project implements AXI-based matrix multiply accelerator.

accelerator verilog systemverilog hardware-designs hardware-acceleration axi xsim vivado-simulator hardware-accelerator uvm-verification matrix-multiply-accumulate ai-accelerator

Updated Aug 27, 2026
SystemVerilog

amirah-sri / all_verilog

Star

I am trying to develop my skills through daily practice and consistency.

verilog vivado vlsi verilog-hdl verilog-programs verilog-project verilog-code vivado-simulator

Updated Jul 31, 2024
Verilog

anr2311 / I2C_State_Machine

Star

This repo contains an I2C transaction state machine modelled in Verilog targeted for the Zynq Zedboard

i2c-bus vivado-simulator

Updated Nov 23, 2024
Verilog

mukund01001 / i2c-uvm-verification

Star

UVM-based verification of an I2C master controller with RTL design, waveform analysis, and Vivado synthesis

i2c verification vivado systemverilog vlsi questasim uvm vivado-hls rtl-design vivado-simulator uvm-verification systemverilog-test-bench rtl-design-and-verification

Updated Apr 7, 2026
SystemVerilog

TahirZia-1 / Digital-Clock-Verilog

Star

This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.

fpga simulation verilog synthesis vivado systemverilog fpga-soc verilog-hdl 7segment systemverilog-hdl digitalclock nexys4ddr fpga-programming vivado-simulator

Updated Feb 28, 2025
Tcl

Raveem13 / VivadoXSIM-UVM_verification

Star

This repository showcases my hands-on SystemVerilog UVM verification using Xilinx Vivado XSIM, focusing on real-world RTL verification, debugging, coverage, and regression scenarios.

coverage-reports vivado systemverilog hdl asic-verification xsim vivado-simulator uvm-verification

Updated Mar 10, 2026
CSS

VRM21-Studios / VRM21-DWT-Module-FPGA

Star

RTL implementation of a configurable single-stage DWT and IDWT accelerator with AXI4-Stream, AXI4-Lite coefficient reconfiguration, fixed-point Q15 processing, and support for software-controlled multi-level wavelet decomposition on FPGA.

verilog vivado systemverilog dwt wavelet wavelet-transform axi-stream systemverilog-simulation vivado-simulator idwt axi-lite discrete-wavelet-transform qmf systemverilog-test-bench symlets verilog-hd

Updated Sep 2, 2026
Verilog

VRM21-Studios / VRM21-RTL-Utilities

Star

This repository contains basic modules that will be frequently used in other repositories on VRM21-Studios

ram dsp verilog vivado systemverilog fifo verilog-hdl axi-stream systemverilog-simulation vivado-simulator axi-lite systemverilog-test-bench

Updated Sep 7, 2026
Verilog

Najid-Villana / KNN-Classifier-in-Verilog

Star

This project is build during The Digital IC Design and Verification Training sponsored by Government of Pakistan. This project shows a KNN algorithm applied using verilog and Vivado.

vivado knn fpga-programming vivado-simulator

Updated Jul 27, 2026
C

TahirZia-1 / UART

Star

A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.

simulation rtl verilog vivado uart systemverilog uart-verilog fpga-soc testbench verilog-hdl fpga-board vivado-hls nexys4ddr verilog-project uart-transmitter uart-receiver fpga-programming vivado-simulator

Updated Feb 28, 2025
SystemVerilog

Navigation Menu

vivado-simulator

Here are 30 public repositories matching this topic...

suoto / hdl_checker

Arjun-Narula / Traffic-Light-Controller-using-Verilog

wyvernSemi / mem_model

arhamhashmi01 / Axi4-lite

esynr3z / pyhdlsim

Ross0907 / Vivado-WDB-Waveform-Converter

mzh330521 / SublimeLinter-contrib-xsim

RipperJ / VerilogExpr2NAND-NOR

Ammar-Bin-Amir / SystemVerilog_Practice

VRM21-Studios / VRM21-NPU-Series

Raveem13 / axi-matrix-accelerator

amirah-sri / all_verilog

anr2311 / I2C_State_Machine

mukund01001 / i2c-uvm-verification

TahirZia-1 / Digital-Clock-Verilog

Raveem13 / VivadoXSIM-UVM_verification

VRM21-Studios / VRM21-DWT-Module-FPGA

VRM21-Studios / VRM21-RTL-Utilities

Najid-Villana / KNN-Classifier-in-Verilog

TahirZia-1 / UART

Add this topic to your repo