IC implementation of Systolic Array for TPU
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Oct 21, 2024 - Verilog
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asic-verification
Here are 46 public repositories matching this topic...
Awesome ASIC design verification
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Feb 9, 2022
VIP for AXI Protocol
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May 24, 2022 - SystemVerilog
Digital Design Equivalence Checking
asic fpga verification eda formal-verification semiconductor sec asic-verification lec asic-design chip-design equivalence-checking slec agentic-chip-design-verification
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Sep 22, 2026 - C++
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a logic simulation. and drive a memory mapped bus
python c fpga cpp processor vhdl logic verification dpi verilog systemverilog pli vpi codesign simulation-element asic-verification logic-simulation dpi-c cosimulation vhpidirect
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Feb 12, 2026 - VHDL
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be …
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Dec 3, 2023 - Verilog
A custom AI chip to be taped out soon!
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Dec 20, 2025 - Python
Quasar 2.0: Chisel equivalent of SweRV-EL2
scala processor chisel riscv rtl chisel3 open-source-hardware verilator asic-verification axi4 ahb-lite asic-design swerv swerv-el2
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Apr 13, 2021 - Scala
LLVM based HLS library for HWToolkit (hardware devel. toolkit)
fpga compiler hls llvm vhdl verification verilog z3 abc systemverilog systemc circuit-analysis asic-verification fpga-programming asic-design hwt logical-syntesis
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Sep 20, 2026 - Python
Systemverilog and UVM exercises inspired by ziglings
asic verification systemverilog uvm systemverilog-simulation asic-verification uvm-verification systemverilog-test-bench systemverilog-constraint uvm-testbench
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Aug 23, 2026 - SystemVerilog
Hdl is a tool for easing the work with hardware description languages.
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Dec 12, 2022 - Go
The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
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May 6, 2023 - VHDL
BDD Gherkin implementation in native SystemVerilog, based on UVM.
asic fpga bdd bdd-specs rtl verilog systemverilog uvm verilog-hdl bdd-framework asic-verification design-verification asic-design rtl-design soc-design soc-verification uvm-verification
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Nov 16, 2024 - SystemVerilog
Open-source desktop workspace for IC design — schematic capture, analog optimization, SPICE/RTL simulation, synthesis, and digital implementation in one Qt app.
python design asic eda schematic spice ic klayout ngspice analog-design asic-verification asic-design sky130 gf180mcu analog-design-automation
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Sep 22, 2026 - Python
Application Specific Integrated Circuit(ASIC)
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Jun 7, 2018 - SystemVerilog
EVPIX-RV32: 5-Stage Custom RISC-V SoC with Integrated IPU and TinyML Support for Real-Time Edge-Vision AI Acceleration: RTL-to-GDSII Design, Verification, Basys-3 Artix-7 FPGA Prototyping and SkyWater 130-nm CMOS ASIC was implementation
linux makefile systemverilog bash-script verilog-hdl yosys asic-verification openroad asic-design rtl-design fpga-prototyping rtl-verification rtl-to-gdsii sky130-pdk
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Sep 7, 2026 - SystemVerilog
An IDE for full RTL to GDSII ASIC design flow, Easier for beginners, Faster for experts, Built for the Open Hardware movement
ide yosys iverilog netgen lvs drc asic-verification openroad asic-design rtl-design openlane rtl-to-gdsii magicvlsi
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Sep 13, 2026 - C++
Made Million Instruction Per Second Processor
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Feb 24, 2018
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