sky130-pdk

EVPIX-RV32: 5-Stage Custom RISC-V SoC with Integrated IPU and TinyML Support for Real-Time Edge-Vision AI Acceleration: RTL-to-GDSII Design, Verification, Basys-3 Artix-7 FPGA Prototyping and SkyWater 130-nm CMOS ASIC was implementation

RTL to GDSII implementation of a parameterized Universal Counter using OpenLane and SKY130

Synthesizable RV32IM Audio SoC featuring a centralized AMBA AXI4-Lite Router Matrix, AXI-to-APB Bridge, 1KB Data SRAM, and PWM engine. Timing-closed and physical layout verified via OpenLane (Sky130).

End-to-End ASIC Design of an 8×32 Synchronous FIFO featuring Verilog RTL design, assertion-based verification in Vivado, and RTL-to-GDSII implementation using OpenLane with the SKY130 PDK.

Simple Systolic array implementation

Open-source RTL-to-GDS ASIC design flow using Yosys, OpenROAD and SKY130, with scripted implementation, verification and reproducible design stages.

Fixed-point MAC accelerator designed to study ASIC timing closure, pipelining, and accumulation feedback in Sky130.

Open Integrated Circuit Library — a searchable catalog of silicon-proven IC designs from open PDKs (SKY130, IHP SG13G2, GF180). Auto-discovers and classifies designs from GitHub/GitLab.

Design of a 10-bit R-2R DAC using the open-source SkyWater 130nm PDK. Includes schematics, layout files, and a Python environment for metric evaluation (for educational purposes).

RTL-to-GDSII physical design flow of PicoRV32a RISC-V processor using OpenLANE and Sky130 PDK. Completed under NASSCOM FutureSkills Prime program. Synthesis, floorplan, placement, CTS, routing, DRC/LVS clean, GDSII generated.

Parameterized Serial-Parallel Multiplier implemented in Verilog and taken through a complete RTL-to-GDSII ASIC flow using OpenLane, Yosys, OpenROAD, OpenSTA, and SKY130, with post-RCX STA, power analysis, DRC, LVS, antenna verification, and GDSII generation.

Timing-aware 2-stage pipelined MAC implemented from SystemVerilog RTL through ASIC physical design and GDSII using OpenLane/OpenROAD and SKY130.

Automated SKY130 DRC flow using KLayout, Python, and TCL to run custom design-rule checks, parse XML results, and generate an HTML violation dashboard.

Data-driven EDA and ML-based predictive modelling of real VLSI design metrics from an OpenLane RTL-to-GDSII flow. 8-bit ALU on Sky130 PDK.

Complete RTL-to-GDSII implementation of a RISC-V based SoC subsystem with AXI4-Lite interconnect, integrating PicoRV32, ROM, SRAM, and UART using SKY130, OpenLane, OpenROAD, Yosys, and OpenSTA.

8-bit Signed Radix-4 Modified Booth Multiplier with 16-bit Carry Lookahead Adder | RTL to GDSII | Verilog | OpenLane | Vivado | Cadence

Complete RTL-to-GDSII implementation of a parameterizable 8-bit ALU using Verilog, Yosys, OpenSTA, OpenLane, Magic, KLayout, and the Sky130 Open-Source PDK.