ASIC implementation flow infrastructure, successor to OpenLane
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Updated
Apr 12, 2026 - Python
ASIC implementation flow infrastructure, successor to OpenLane
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
Open source compliance automation for SOC 2, GDPR, ISO27001, NIST 800-53, and more
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130
Gate-level visualization generator for SKY130-based chip designs.
Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah
the openlane ui - holds the openlane console and storybook
🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation
CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.
This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.
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