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The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

Updated Mar 25, 2026
Python

efabless / caravel

Star

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

magic yosys caravel picorv32 openroad vexriscv openram sky130

Updated Feb 26, 2025
Verilog

efabless / caravel_mpw-one

Star

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

magic yosys caravel picorv32 openroad openram sky130

Updated Feb 22, 2022
Verilog

efabless / clear_old

Star

CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.

open-source fpga caravel openfpga openlane efpga chipignite

Updated Mar 19, 2022
Verilog

0x01be / rudder

Star

Learn, share and collaborate on ASIC design using open tools and technologies

magic eda klayout caravel pdk

Updated Dec 27, 2020
Dockerfile

neevany / caravel-on-heroku

Star

One-button Heroku deploy for the Caravel data exploration platform.

heroku superset airbnb dataexplorer caravel

Updated Oct 30, 2016
Python

kbeckmann / caravel-pll-calculator

Sponsor

Star

PLL configuration generator for the Caravel management core

caravel skywater openlane

Updated May 7, 2021
Python

FPGA-Research / FABulous_board

Star

A PCB created for FABulous FPGAs, based on the caravel board.

pcb caravel fpga-board

Updated Jul 18, 2025
Python

CDragon123-code / caravel-sha256-accelerator

Star

SHA-256 accelerator on Caravel SoC (SkyWater 130nm) - open-source RTL-to-GDSII signoff flow

asic verilog sha-256 caravel physical-design open-source-eda openlane sky130

Updated Aug 27, 2026
Verilog

efabless / caravel_ibex

Star

An example project that utilizes caravel user space for an ibex based SoC

soc caravel ibex openlane mpw-two

Updated Aug 16, 2021
Verilog

Bhavuk-HDL / custom-asic

Star

Eight different verilog projects are combined to creat a big custom asic project.

asic ram verilog spi sram uart nand2tetris fifo hdl risc-v caravel

Updated Jan 8, 2023
Verilog

truong92cdv / aes

Star

Implementing an AES ecnryption IP Core with Caravel Platform

cryptography asic aes soc caravel wishbone openlane

Updated Sep 10, 2025
Verilog

Mummanajagadeesh / fir-accel-caravel-soc

Star

Mixed-signal FIR accelerator SoC on Caravel/Sky130A — CIC decimator, 8-tap programmable FIR filter, PWM DAC, Wishbone CSR

asic dsp rtl verilog vlsi caravel openlane sky130

Updated Apr 1, 2026
Verilog

DivyamGoyal-github / RISC_V-SoC-Tapeout-Program_VSD_Caravel_IITGN_Phase2

Star

This repository contains documentation and relevant materials for the RISC-V SoC Tapeout Program, a collaborative initiative between IIT Gandhinagar, VLSI System Design (VSD), and other prominent organizations in the field of semiconductor design.

simulation verification rtl verilog gls synopsys risc-v caravel pdk chip-design functional-simulation scl180nm

Updated Jan 5, 2026
Verilog

ShekharShwetank / RISC-V_Reference_SoC_Tapeout_Program_Phase_2

Star

RISC-V Reference SoC Design and Tapeout Program Phase 2 personal documentation

asic synopsys risc-v caravel asic-design sky130 system-on-chip-design scl180nm

Updated Feb 19, 2026
Verilog

Pa1mantri / VSDSquadron_RTL_GDSII

Star

Verified a physically implemented 32-bit Wishbone slave wrapper using mixed-level simulation, successfully integrating the Gate-Level Netlist within the full Caravel RTL SoC environment to ensure system-level compatibility.

rtl gls soc caravel mixed-level-simulation rtl2gdsii

Updated Jun 16, 2026
Verilog

hemachandhran / Open-Source-ASIC-Design-RTL-to-GDSII

Star

Hands-on open-source ASIC design portfolio documenting the complete RTL-to-GDSII flow, SoC verification, and gate-level simulation using OpenLane, OpenROAD, SKY130, Caravel, and VSDSquadron.

asic tcl rtl gls orfs soc risc-v caravel physical-design openroad openlane sky130 rtl-gds vsdsquadron

Updated Jul 2, 2026
Verilog

ayoub-ac / wishbone-fpga-core

Star

Wishbone B4 master+slave IP core in SystemVerilog. Classic + pipelined modes, burst support, alt to AXI for open-hardware (Caravel/LiteX/OpenROAD).

fpga bus verilog systemverilog yosys caravel wishbone verilator litex ip-core openroad wishbone-b4

Updated May 10, 2026
SystemVerilog

truong92cdv / caravel_aes_accelerator

Star

Implementing an AES ecnryption IP Core with Caravel Platform

asic aes verilog caravel openlane

Updated Aug 16, 2025
Verilog

erikvanzijst / wrapped_pong

Star

An ASIC running Pong.

asic fpga electronics verilog ic silicon caravel

Updated Dec 9, 2021
Verilog

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caravel

Here are 22 public repositories matching this topic...

The-OpenROAD-Project / OpenLane

efabless / caravel

efabless / caravel_mpw-one

efabless / clear_old

0x01be / rudder

neevany / caravel-on-heroku

kbeckmann / caravel-pll-calculator

FPGA-Research / FABulous_board

CDragon123-code / caravel-sha256-accelerator

efabless / caravel_ibex

Bhavuk-HDL / custom-asic

truong92cdv / aes

Mummanajagadeesh / fir-accel-caravel-soc

DivyamGoyal-github / RISC_V-SoC-Tapeout-Program_VSD_Caravel_IITGN_Phase2

ShekharShwetank / RISC-V_Reference_SoC_Tapeout_Program_Phase_2

Pa1mantri / VSDSquadron_RTL_GDSII

hemachandhran / Open-Source-ASIC-Design-RTL-to-GDSII

ayoub-ac / wishbone-fpga-core

truong92cdv / caravel_aes_accelerator

erikvanzijst / wrapped_pong

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