A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.
Deterministic real-time emulation framework for flowing-fuel MSRE transients with delayed core/BOP coupling and FPGA-oriented split-kernel execution.
LLM-Aided FPGA Design for Signal Processing Applications
Agent skill for AMD/Xilinx Vitis HLS generation and FPGA design workflows.
Advanced multi-band GNSS SDR front-end implementation in an RFSoC integrated circuit. GPL-3.0 license
DaCH: dataflow cache for high-level synthesis.
LLM-Aided FPGA Design Optimization
Mixing HLS and Backend Versions in Vitis
Hardware-accelerated CNN on Xilinx Zynq-7020 FPGA for real-time Person/Object detection. Built with Vitis HLS, Vivado & PYNQ — no Vitis AI, no FINN.
FPGA Acceleration for the LoFreq variant caller
Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)
Deep Learning Aided Radar Signal Processing on Zynq SoCs for Doppler Estimation with hardware (Zynq SoC IPs)
50.7x latency-optimized heterogeneous Vision Transformer (DeiT) hardware accelerator built on the Xilinx ZCU104 FPGA using DPU + custom HLS IPs.
Xilinx Tools Tutorials
Vitis (Vivado) HLS Examples
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
One sweep, all segments: a line segment detector that reads the image exactly once — O(width) memory, integer-only streaming core — with HLS and Verilog RTL running live on an FPGA at 1080p30.
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