SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
HLS-based framework to accelerate the implementation of 2-D DP kernels on FPGA
CMake for Xilinx Vivado/Vitis
Xilinx Tools Tutorials
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
Zynq-7000 and Zynq UltraScale+ PS side drivers for SdCard.
Carry-Lookahead 16-bits Adder (CLA16) computes sums by rapidly determining carry bits through parallel processing.
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
Bare-metal firmware development using Xilinx Vivado & Vitis and PetaLinux porting on the Xilinx Zynq-7000 SoC architecture (ZedBoard & Zybo Z7). Developed during my Summer Research Internship at the Variable Energy Cyclotron Centre (VECC) for particle accelerator instrumentation and LLRF control applications
A TFTP server running on Zynq-7000
High-throughput Sparse Matrix–Vector Multiply (SPMV) accelerator for the Xilinx Alveo U280, redesigned from Serpens A16 into a fully Vitis HLS dataflow kernel with 24 HBM channels and improved memory and parallelism.
FPGA-based hardware-accelerated, parallelized, and highly optimized solution for solving the Travelling Salesperson Problem (TSP) using Xilinx Zynq-7000 on a Digilent Zybo Z7-10 board, featuring FreeRTOS for real-time task management.
(Arch Linux package) Xilinx FPGA/CPLD design suite downgraded to version 2019.2
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