Deterministic real-time emulation framework for flowing-fuel MSRE transients with delayed core/BOP coupling and FPGA-oriented split-kernel execution.
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Aug 26, 2026 - Python
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vitis-hls
Here are 6 public repositories matching this topic...
Agent skill for AMD/Xilinx Vitis HLS generation and FPGA design workflows.
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Aug 14, 2026 - Python
SGBM source-code analysis and operator notes extracted from FPGA_HKCamera_SGBM
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Jul 20, 2026 - Python
Hand-written SystemVerilog SIMD core (Fall 2025) followed by an Allo DSL/HLS redesign adding INT8 GEMM, ReLU, and fusion kernels (Spring 2026), targeting the Nexys A7.
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May 1, 2026 - Python
Automated Simulink-to-FPGA pipeline in Python: generates HLS-ready C from a discrete-time power system model (Emergency Diesel Generator), runs Vitis HLS synthesis on Zynq-7000 (xc7z020clg400-1) for 5 step sizes (5-100 us), and compares hardware execution to Simulink reference. 5.5x-6x speedup, 1e-11 to 1e-12 error.
python automation fpga zynq hls rtl xilinx simulink vivado power-systems high-level-synthesis mathworks embedded-coder hardware-simulation vitis-hls
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May 8, 2026 - Python
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