LLM-Aided FPGA Design Optimization
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Jun 4, 2025 - C
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vitis-hls
Here are 6 public repositories matching this topic...
FPGA Acceleration for the LoFreq variant caller
bioinformatics fpga hls probability-distribution xilinx variant-calling bioinformatics-tool lofreq vitis-hls poisson-binomial-distribution counting-models
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Oct 18, 2025 - C
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado microblaze axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls
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Dec 3, 2023 - C
FPGA implementation of a quantized LeNet-5 CNN accelerator combining High-Level Synthesis (Vitis HLS) and hand-written RTL (VHDL) for an optimized streaming convolution architecture.
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May 10, 2026 - C
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Mar 23, 2023 - C
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