AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Updated
Jul 24, 2025 - SystemVerilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Network on Chip Implementation written in SytemVerilog
Code generation tool for control and status registers
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
Control and status register code generator toolchain
Simple single-port AXI memory interface
OPAE porting to Xilinx FPGA devices.
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction.
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
Open-Source AXI4 DMA Engine in SystemVerilog and Chisel
XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA
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