rggen rggen · Discussions · GitHub

Discussions

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How to initialize non sequential bit field register block

alejandro-castro-ortegon asked Jan 31, 2025 in Q&A · Closed · Unanswered

8
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shadow registers

gkamendje73 asked Dec 4, 2024 in Q&A · Closed · Unanswered

4
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how to add an update path to a register generated from rggen

nijie001 asked Jul 12, 2024 in Q&A · Unanswered

2
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Is there a possibility or any option to turn off interface instance?

p1680 asked Jun 26, 2024 in Q&A · Closed · Unanswered

2
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learn rggen,

nijie001 asked Jun 10, 2024 in Q&A · Closed · Unanswered

11
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Welcome to RgGen Discussions!

taichi-ishitani started Dec 9, 2020 in General

1
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Different Interface for Software and RTL

SzymonHitachi asked Jun 6, 2024 in Q&A · Answered

5
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[question] Passthrough address

SzymonHitachi asked May 8, 2024 in Q&A · Closed · Answered

6
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Disable SV generation when running VHDL code generation

SzymonHitachi asked Apr 29, 2024 in Q&A · Closed · Answered

4
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How to use parameter from my IP

gkamendje73 asked Mar 17, 2024 in Q&A · Unanswered

5
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Repeat register multiple times

SzymonHitachi asked Feb 13, 2024 in Q&A · Closed · Answered

10
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Improvement Ideas

cookacounty started Feb 19, 2021 in Ideas

27
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axi4lite interface not generated

abhiram1 asked Apr 19, 2023 in Q&A · Answered

11
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PyUVM RAL

SikoVerilog started Feb 9, 2023 in Ideas

1
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v0.27.0

taichi-ishitani started Jul 5, 2022 in General

6
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register hole issue

mk1057493329 asked Apr 8, 2022 in Q&A · Answered

4
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How to get Started Contributing?

cookacounty asked Feb 22, 2021 in Q&A · Unanswered

2