Click Bait Filter Backend (Prototype_Server)

This repository contains the RTL code of a DVP (Digital Video Port) TX Controller with AXI4 interface in the application layer.

The Atfox exTensible Interface (ATI) is a on-chip communication bus protocol, which support for ATI System Bus Structure

APB Interfacing logic for Propell

RTL code for DMA controller

Book World: MERN stack app for book reviews & management. Users explore books, leave reviews & build favorites lists. Admins manage book collection and users.

Verilog AXI stream components for FPGA implementation

AXI协议规范中文翻译版

This repo will contain the Verilog code implementation of various protocols that fall within AMBA protocol family such as APB, AHB, AXI and so on. I will implement it in parallel with learning theory. If possible I will also use UVM and system verilog to verify the functionality of the code once I finish learning system verilog and concepts of uvm

A Web Video Streaming Application

Knowledge hub for digital interfaces

Build an open source, extremely simple DMA.

Functional Bus Description Language compiler backend for Advanced Microcontroller Bus Architecture 5 (AMBA5) specifications.

Functional Bus Description Language compiler front-end written in Go.

Реализация AXI интерфейса на SystemVerilog

Reusable AXI Universal Verification Component built with SystemVerilog and UVM. Integrates into any testbench to accelerate design verification with modular agents, monitors, drivers, coverage, and scoreboard.

UVM based Verification of SPI_Protocol and I2C_Protoccol. A Serial intra System Communication Peripheral Protocol

Spotify Clone With Reactjs