The Atfox exTensible Interface (ATI) is a on-chip communication bus protocol, which support for ATI System Bus Structure

Click Bait Filter Backend (Prototype_Server)

APB Interfacing logic for Propell

Book World: MERN stack app for book reviews & management. Users explore books, leave reviews & build favorites lists. Admins manage book collection and users.

Реализация AXI интерфейса на SystemVerilog

AXI协议规范中文翻译版

Verilog AXI stream components for FPGA implementation

This repo will contain the Verilog code implementation of various protocols that fall within AMBA protocol family such as APB, AHB, AXI and so on. I will implement it in parallel with learning theory. If possible I will also use UVM and system verilog to verify the functionality of the code once I finish learning system verilog and concepts of uvm

A Web Video Streaming Application

Build an open source, extremely simple DMA.

Functional Bus Description Language compiler backend for Advanced Microcontroller Bus Architecture 5 (AMBA5) specifications.

Knowledge hub for digital interfaces

Functional Bus Description Language compiler front-end written in Go.

Spotify Clone With Reactjs

Node.js app for processing outage data for KrakenFlex. Fetches, filters, and posts outage data based on site requirements. Built with Express, Axios, and TypeScript; tested with Jest. Includes functionality for fetching outages, filtering by device and date, and posting processed data to an API.

UVM based Verification of SPI_Protocol and I2C_Protoccol. A Serial intra System Communication Peripheral Protocol

Reusable AXI Universal Verification Component built with SystemVerilog and UVM. Integrates into any testbench to accelerate design verification with modular agents, monitors, drivers, coverage, and scoreboard.

Verilog header for easier AXI interface declaration & connection