Click Bait Filter Backend (Prototype_Server)

A presentation about Advanced Microcontroller Bus Architecture

VHDL UART Module with AXI interface

Full Stack CoffeeShop Digital Menu Cart.

Verilog header for easier AXI interface declaration & connection

🏄 Custom IP for vector operations

The Atfox exTensible Interface (ATI) is a on-chip communication bus protocol, which support for ATI System Bus Structure

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Synchronous and Asynchronous FIFO with AXI interface

Extract AXI (Full, Lite and Stream) interfaces from Verilog source files

Сервис по подбору доступного жилья.

PYNQ-Z1/Z2 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx

APB Interfacing logic for Propell

AXI DMA with Petalinux

FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.

just some files that show one simple way to simulate some axi cycles.

Statistics Acquisition Module on Verilog

Build an open source, extremely simple DMA.

FIR IP with AXI-Lite & AXI_stream

Learning Resources for AXI made by self