VHDL UART Module with AXI interface

🏄 Custom IP for vector operations

Click Bait Filter Backend (Prototype_Server)

This repository contains the RTL code of a DVP (Digital Video Port) TX Controller with AXI4 interface in the application layer.

A presentation about Advanced Microcontroller Bus Architecture

Synchronous and Asynchronous FIFO with AXI interface

Set of useful tools around the Axie infinity game.

The Atfox exTensible Interface (ATI) is a on-chip communication bus protocol, which support for ATI System Bus Structure

Verilog header for easier AXI interface declaration & connection

Extract AXI (Full, Lite and Stream) interfaces from Verilog source files

APB Interfacing logic for Propell

AXI DMA with Petalinux

Full Stack CoffeeShop Digital Menu Cart.

FIR IP with AXI-Lite & AXI_stream

RTL code for DMA controller

FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.

Book World: MERN stack app for book reviews & management. Users explore books, leave reviews & build favorites lists. Admins manage book collection and users.

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Verilog AXI stream components for FPGA implementation