🏄 Custom IP for vector operations

AXI DMA with Petalinux

VHDL UART Module with AXI interface

Synchronous and Asynchronous FIFO with AXI interface

Verilog header for easier AXI interface declaration & connection

The Atfox exTensible Interface (ATI) is a on-chip communication bus protocol, which support for ATI System Bus Structure

Click Bait Filter Backend (Prototype_Server)

A presentation about Advanced Microcontroller Bus Architecture

This repository contains the RTL code of a DVP (Digital Video Port) TX Controller with AXI4 interface in the application layer.

Extract AXI (Full, Lite and Stream) interfaces from Verilog source files

APB Interfacing logic for Propell

Full Stack CoffeeShop Digital Menu Cart.

FIR IP with AXI-Lite & AXI_stream

RTL code for DMA controller

Book World: MERN stack app for book reviews & management. Users explore books, leave reviews & build favorites lists. Admins manage book collection and users.

Реализация AXI интерфейса на SystemVerilog

Standalone IP with ARM-AMBA/AXI capable device. Enables sending and receiving data via SpaceWire protocol. Tested on Xilinx FPGA (ZYNQ).

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A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.