Synchronous and Asynchronous FIFO with AXI interface
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Nov 20, 2019 - SystemVerilog
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axi
Here are 89 public repositories matching this topic...
🏄 Custom IP for vector operations
zynq vector vhdl vivado hardware-designs hdl custom-ip fpga-accelerator axi vitis axi-lite vector-operation vector-ops vector-operations
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Aug 31, 2024 - VHDL
The Atfox exTensible Interface (ATI) is a on-chip communication bus protocol, which support for ATI System Bus Structure
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Nov 24, 2023 - C
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Sep 16, 2023 - JavaScript
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
design fpga communication-protocol digital hardware electronics processor master-slave verilog vivado floating-point intellectual-property c-programming integrated-circuits microblaze axi interconnect microelectronics vitis arty-s7
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Apr 13, 2024 - VHDL
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls axi-memory-mapped
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Nov 21, 2023 - TeX
Сервис по подбору доступного жилья.
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Sep 16, 2023 - JavaScript
PYNQ-Z1/Z2 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx
python jupyter-notebook xilinx uart pynq pynq-hardware-overlay xilinx-vivado axi pynq-z1 xilinx-zynq pynq-z2
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May 1, 2020 - Tcl
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