axi

Here are 18 public repositories matching this topic...

yasnakateb / VectorOps

🏄 Custom IP for vector operations

zynq vector vhdl vivado hardware-designs hdl custom-ip fpga-accelerator axi vitis axi-lite vector-operation vector-ops vector-operations

Updated Aug 31, 2024
VHDL

javos65 / APB_Slave_Interfacing

Star

APB Interfacing logic for Propell

adc lattice pwm propel risc-v axi apb

Updated Jan 5, 2025
VHDL

Florin623 / AXI-Lite-Slave-FPU-IP

Star

FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.

Updated Apr 13, 2024
VHDL

vacagonzalo / soc-workflow-vhdl

Star

Example workflow project for VHDL development.

workflow vhdl tcl vivado axi axi-bus tcl-scripts cocotb cocotb-testing

Updated Feb 18, 2023
VHDL

vedranMv / axi_spi_master

Star

IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)

spi vhdl-modules axi axi-spi ip-core

Updated Jul 12, 2017
VHDL

AranelLindi / AXI_SpaceWire_IP

Star

Standalone IP with ARM-AMBA/AXI capable device. Enables sending and receiving data via SpaceWire protocol. Tested on Xilinx FPGA (ZYNQ).

arm zynq xilinx spacewire soc axi

Updated Jul 12, 2024
VHDL

narendiran1996 / AXILearning

Star

Learning Resources for AXI made by self

axis axi axi-master

Updated Jun 4, 2021
VHDL

plasoc / axiplasma

Star

AXI/MIPS SoC developed in VHDL with FreeRTOS port. Capable of running either preemptively or cooperatively.

c real-time mips vhdl operating-system freertos xilinx vivado system-on-chip axi amba

Updated Mar 19, 2018
VHDL

pkill37 / fpga-linreg

Star

FPGA benchmark of vectorized gradient descent on linear regression

fpga linear-regression vhdl xilinx gradient-descent microblaze axi axi-stream

Updated Aug 13, 2018
VHDL

mrengineer / Zynq7000_simpleDMA_IRQ_vivado_linux_userspace

Star

Complete project in Vivado 2022.1 + userspace app for petalinux. Loopback AXI simple DMA transfer.

petalinux dma axi

Updated May 20, 2023
VHDL

pothosware / PothosFPGA

Star

Pothos FPGA computational offload and buffer integration support

fpga stream xilinx axi pothos pothos-framework

Updated Jun 12, 2015
VHDL

Kampi / OV7670

Sponsor

Star

FPGA interface and driver for an OV7670 camera sensor.

fpga vhdl imageprocessing fpga-soc xilinx-fpga axi ov7670 axi-stream

Updated Aug 28, 2023
VHDL

pedrovt / cr-labs

Star

Labs of the Reconfigurable Computing course, University of Aveiro

fpga vhdl xilinx fpga-soc axi reconfigurable-computing

Updated Jun 2, 2020
VHDL

Florin623 / AXI-Lite-Slave-FFT-IP

Star

3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.