🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

🏄 Custom IP for vector operations

Standalone IP with ARM-AMBA/AXI capable device. Enables sending and receiving data via SpaceWire protocol. Tested on Xilinx FPGA (ZYNQ).

3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.

FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.

FPGA interface and driver for an OV7670 camera sensor.

Complete project in Vivado 2022.1 + userspace app for petalinux. Loopback AXI simple DMA transfer.

Example workflow project for VHDL development.

Learning Resources for AXI made by self

Labs of the Reconfigurable Computing course, University of Aveiro

ASIC for executing vectorized gradient descent on linear regression problems.

AXI/MIPS SoC developed in VHDL with FreeRTOS port. Capable of running either preemptively or cooperatively.

IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)

VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.

Pothos FPGA computational offload and buffer integration support