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axi
Here are 18 public repositories matching this topic...
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
simulation vhdl verilog questasim ghdl avalon memory-model test-bench pli verilog-components verilator axi nvc dpi-c cosimulation vivado-simulator verilog-testbenches
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Jul 8, 2025 - VHDL
VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
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Mar 24, 2017 - VHDL
IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)
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Jul 12, 2017 - VHDL
🏄 Custom IP for vector operations
zynq vector vhdl vivado hardware-designs hdl custom-ip fpga-accelerator axi vitis axi-lite vector-operation vector-ops vector-operations
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Aug 31, 2024 - VHDL
FPGA benchmark of vectorized gradient descent on linear regression
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Aug 13, 2018 - VHDL
3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
design communication-protocol pipeline digital hardware electronics signal-processing processor master-slave verilog fft vivado intellectual-property c-programming integrated-circuits microblaze axi interconnect microelectronics vitis
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Apr 13, 2024 - VHDL
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
design fpga communication-protocol digital hardware electronics processor master-slave verilog vivado floating-point intellectual-property c-programming integrated-circuits microblaze axi interconnect microelectronics vitis arty-s7
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Apr 13, 2024 - VHDL
Example workflow project for VHDL development.
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Feb 18, 2023 - VHDL
FPGA interface and driver for an OV7670 camera sensor.
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Aug 28, 2023 - VHDL
UVM based Verification of SPI_Protocol and I2C_Protoccol. A Serial intra System Communication Peripheral Protocol
c fpga i2c verilog spi vivado systemverilog uvm verdi microblaze axi hardware-description-language basys3-fpga synopsys-vcs
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Jul 24, 2025 - VHDL
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