This repo will contain the Verilog code implementation of various protocols that fall within AMBA protocol family such as APB, AHB, AXI and so on. I will implement it in parallel with learning theory. If possible I will also use UVM and system verilog to verify the functionality of the code once I finish learning system verilog and concepts of uvm

Build an open source, extremely simple DMA.

This repository contains the RTL code of a DVP (Digital Video Port) TX Controller with AXI4 interface in the application layer.

一个基于AXI的DMA

FIR IP with AXI-Lite & AXI_stream

just some files that show one simple way to simulate some axi cycles.

An implementation of AMBA AXI4Lite on an FPGA using verilog

This project is part of my master's thesis. Source code shared for the publication "StreamIF - AXI4 Memory Mapped to AXI4 Stream Interface Library"

RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction.

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

SD-Card controller, using either SPI, SDIO, or eMMC interfaces