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vlsi-project

Here are 12 public repositories matching this topic...

mihir8181 / VLSI-Design-Digital-System

This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

Updated Mar 22, 2019

hibagus / 64pointFFTProcessor

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

signal-processing fast-fourier-transform digital-signal-processing vlsi-physical-design fpga-accelerator vlsi-design vlsi-project

Updated May 20, 2020
Verilog

karthik-r-rao / VLSI_Physical_Design_Tool

A simple tool to demonstrate the physical design steps of VLSI Design Flow.

vlsi vlsi-physical-design vlsi-design vlsi-project vlsi-cad

Updated Dec 13, 2020
Python

tharunchitipolu / SHA-256-Verilog-HDL

SHA-2 (Secure Hash Algorithm 2), of which SHA-256 is a part, is one of the most popular hashing algorithms out there.

security cryptography hardware vlsi verilog-hdl sha256-hash vlsi-project

Updated Jun 9, 2021
Verilog

gmurro / VLSI

Very Large Scale Integration project for CDMO class at @unibo

satisfiability-solver satisfiability-modulo-theories constraint-programming sat vlsi-project

Updated Aug 31, 2021
Python

harshithsn / SCOAP-Controllability-and-Observability

This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs SCOAP Controllability and Observability of circuit..

vlsi controllability observability vlsi-project scoap scoap-analysis-tool

Updated Nov 12, 2021
Jupyter Notebook

harshithsn / Fault-collapsing-and-Fault-simulation

This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs Dominance fault collapsing, Parallel fault simulation, Deductive fault simulation.

vlsi vlsi-project prallel-fault-simulation fault-collapsing deductive-fault-simulation

Updated Nov 16, 2021
Jupyter Notebook

lolloloschi97 / Very-Large-Scale-Integration

Very Large Scale Integration solved using Costraint Programming and Minizinc

optimization constraint-programming z3-smt-solver vlsi-project minizinc-python

Updated Oct 17, 2022
Jupyter Notebook

tharunchitipolu / Dadda-Multiplier-using-CSA

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

rtl verilog fulladder vlsi multiplier hardware-description-language wallace vlsi-design vlsi-project dadda-tree carry-save-adder fast-multiplication dadda-multiplier tree-multipliers

Updated Jun 6, 2024
Verilog

Kethasriramya2912 / Btech_Projects

I've delved into leveraging my academic prowess to drive projects that contribute to my career advancement.

final-year-project vlsi-design vlsi-project btechprojects rtldesign

Updated Apr 8, 2025
Verilog

VLSI-Design-Verification-Projects

SACHINUR17 / VLSI-Design-Verification-Projects

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

Updated Sep 13, 2025
SystemVerilog

BegangLive / VLSI-Design-Verification-Projects

This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects

protocol verification rtl verilog systemverilog alu modelsim uvm vlsi-physical-design electronics-engineering vlsi-design design-verification vlsi-project system-verilog-testbench

Updated Dec 16, 2025
Stata

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