artix

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Wrapper module for the PicoSoC to support the Digilent Basys 3

verilog xilinx vivado risc-v basys3 picorv32 digilent artix artix-7 picosoc

高性能 AES-128 Verilog 加密核心实现。采用 11 级流水线架构，支持 100MHz 工作频率，并针对 FPGA 引脚限制设计了优化的 32 位多路复用总线接口。设计完全兼容 FIPS-197 标准，兼顾高吞吐量与低资源消耗。

encryption aes-128 verilog artix fpga-programming xc7a35tfgg484-2

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