a high performance library for building cache simulators
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Updated
Nov 29, 2025 - C++
a high performance library for building cache simulators
SST Architectural Simulation Components and Libraries
A low-latency LRU approximation cache in C++ using CLOCK second-chance algorithm. Multi level cache too. Up to 2.5 billion lookups per second.
A C++11 simulator for a variety of CDN caching policies.
Haystack is an analytical cache model that given a program computes the number of cache misses.
A cache simulator, using the C++ language, to simulate a direct-mapped, fully associative and set-associative cache. It has a set of memory reference generators to generate different sequences of references.
A graphics tracing and replay framework to explore system-level effects on heterogeneous CPU+GPU memory systems.
Contains implementations of cache-optimized and external memory algorithms.
Computer architecture related projects
A high-performance cache and memory hierarchy simulator built with modern C++17. Features configurable cache levels, advanced prefetching, MESI protocol, and detailed statistics. Ideal for computer architecture education, research, and performance analysis.
Direct Mapped and N-Way set associative cache Simulator in C/C++ for L1 cache in Processors
An in-depth project focusing on the design and simulation of a split L1 cache in C++. This repository covers MESI protocol operations, comprehensive test cases, and simulation results, showcasing strategies for enhancing cache coherence and performance. This is a class project from ECE 585: Microprocessor System Design at Portland State University
A comprehensive C++20 cache simulator for analyzing memory hierarchy performance with configurable cache levels, replacement policies, and inclusion strategies
PKU computer organization and architecture memory hierarchy simulator LAB
A 3-level cache simulator for SPEC traces with various inclusion and block replacement policies
Simulator for Direct, Associative, Set Associative Mapping Technique in Cache Allocation
C++ Instruction Set Simulator for RISC-V RV32IMC & custom packed SIMD ISA with cache and branch predictor models, C/ASM workloads, and Python analysis tools
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