SST Architectural Simulation Components and Libraries

Dynamic Instrumentation Tool Platform

C++ Instruction Set Simulator for RISC-V RV32IMC & custom packed SIMD ISA with cache and branch predictor models, C/ASM workloads, and Python analysis tools

Ultra-small (<5KB) in-memory cache for Node.js & browsers with TTL, LRU eviction, stale-while-revalidate, stale-if-error, async deduplication (getOrSet), disposal hooks, deep cloning, and zero dependencies.

a high performance library for building cache simulators

CSC3050 Assignment 4 - Fall 2025

🚮 A Google extension that will allow you to delete cookies and everything in cache

Implementation and analysis of cache replacement policies (Random and Least Recently Used) in a C++-based cache simulator. This project explores cache architecture behavior, evaluates eviction strategies, and measures performance metrics such as cache hits, misses, and flush counts.

Arquitecture project for rendering optimizer cache in c++

This project focuses on developing a visual memory simulator using ChampSim, an efficient trace-based simulator for microarchitecture research. Our simulator features a graphical user interface (GUI) designed to display the usage of data cache in real-time, providing an interactive way to understand memory access patterns and cache behaviour.

C++ implementation of computer architecture branch prediction algorithms with comprehensive Python analysis tools. Features static and two-bit dynamic branch predictors, configurable Branch Target Buffer (BTB) with LRU replacement, automated performance testing and visualization of prediction accuracy and processor overhead metrics.

A high-performance cache and memory hierarchy simulator built with modern C++17. Features configurable cache levels, advanced prefetching, MESI protocol, and detailed statistics. Ideal for computer architecture education, research, and performance analysis.

The repository simulates direct-mapped , four way set associative and 8 way set associative cache.

A Java cache memory simulator that models cache hits, misses, reads, and writes with interactive command-line input. Demonstrates set-associative cache behavior and memory block fetching.

Simulador de cache parametrizável desenvolvido em Python para a disciplina de Arquitetura e Organização de Computadores II. Analisa o desempenho de hierarquias de memória com diferentes configurações de cache (nsets, bsize, assoc) e políticas de substituição (Random, FIFO, LRU), calculando métricas de hit/miss e classificando misses.

RISCV Architectural Simulator

Exploring CPU/GPU memory hierarchies, cache modeling, DRAM simulation, GPU programming with CUDA, and near-data processing using PIMeval-PIMbench - CS 6501 CPU/GPU Memory Systems @ UVA Spring '25

A comprehensive C++20 cache simulator for analyzing memory hierarchy performance with configurable cache levels, replacement policies, and inclusion strategies

A two-level cache simulator developed for a computer architecture course. Features physically-indexed, physically-tagged L1/L2 caches with configurable parameters, multiple replacement policies (LRU, FIFO, Random), and detailed performance statistics. Supports USIMM trace files for realistic memory access pattern analysis.

Sistema de gestión de logs de alto rendimiento. Proporciona caché temporal, limpieza automática de logs antiguos y almacenamiento persistente.