KevinWang96 / Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip Star 19 Code Issues Pull requests EE577b-Course-Project verilog-hdl multiprocessor processor-design networkonchip synopsys-dc cadence-ncverilog cadence-conformal Updated May 6, 2020 Verilog
KevinWang96 / EE577b-HW Star 3 Code Issues Pull requests modelsim verilog-hdl synopsys-dc cadence-conformal Updated Apr 3, 2020 Verilog
ShekharShwetank / ASIC_Design Star 2 Code Issues Pull requests ASIC design flow implementation for digital circuits, RTL simulation to physical design using Cadence tools. rtl verilog cadence modus asic-design cadence-incisive cadence-conformal innovus cadence-xcelium rtl-gds genus-synthesis Updated Nov 10, 2025 Verilog
pritam-sethuraman / USB-Core Star 1 Code Issues Pull requests vhdl synopsys formal-verification formality design-vision equivalence-checker cadence-conformal Updated Jun 9, 2023 VHDL