cadence-xcelium

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ShekharShwetank / ASIC_Design

ASIC design flow implementation for digital circuits, RTL simulation to physical design using Cadence tools.

rtl verilog cadence modus asic-design cadence-incisive cadence-conformal innovus cadence-xcelium rtl-gds genus-synthesis

Updated Nov 10, 2025
Verilog

Hampton-bit / fifo_layered_testbench

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Layered SystemVerilog testbench for verifying a parameterized Synchronous FIFO. Includes directed and constrained-random tests, functional coverage, assertions, and scoreboard-based checking.

verification systemverilog functional-verification cadence-xcelium

Updated Jun 24, 2025
SystemVerilog

franklinthony / integrated-circuits-systemverilog

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Exercícios desenvolvidos durante a disciplina Concepção Estruturada de Circuitos Integrados, relacionando os mais diversos assuntos da mesma.

systemverilog system-verilog cadence integrated-circuits cadence-xcelium

Updated Jun 27, 2023
SystemVerilog

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