Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.

Yet another faux-retro game system

Educational project for the Xilinx ZedBoard Zynq-7000 Development Kit

Yet Another Simple Router - a COCOTB verification of the Verilog RTL model example

Module for load configuration from ClockBuilderPro to Si5340 PLL via i2c interface

I worked personally on designing rv32i processor for some of the instructions like add,addi,sub,etc..

This project implements the SHA-256 cryptographic hash function in Verilog. It includes a modular design with separate modules for various components, as well as testbenches written in Python using Cocotb for simulation and verification.