Implement HDMI output using only SystemVerilog and an Analog Devices ADV7513
-
Updated
Feb 20, 2022 - SystemVerilog
#
cyclone-v
Here are 5 public repositories matching this topic...
DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA
ds1302 systemverilog hdl modelsim quartus-prime cyclone-v rtc-module hardware-description-language altera-fpga terasic-de10-standard
-
Updated
Jul 30, 2022 - SystemVerilog
Basic Stopwatch Design using Terasic DE-10 Standard FPGA
systemverilog hdl modelsim quartus-prime cyclone-v hardware-description-language altera-fpga terasic-de10-standard
-
Updated
Jul 30, 2022 - SystemVerilog
A SystemVerilog-based UART (Universal Asynchronous Receiver/Transmitter) module built from scratch using FSM design. Includes baud tick generator, transmitter and receiver FSMs, and simulation testbenches for 8N1 serial communication.
open-source fpga rtl loopback uart altera digital-logic systemverilog hdl serial-communication cyclone-v educational-project intel-quartus hardware-design
-
Updated
Aug 11, 2025 - SystemVerilog
Simple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA
cpu fpga systemverilog hdl modelsim quartus-prime cyclone-v hardware-description-language altera-fpga terasic-de10-standard
-
Updated
Aug 3, 2022 - SystemVerilog
Improve this page
Add a description, image, and links to the cyclone-v topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the cyclone-v topic, visit your repo's landing page and select "manage topics."