OpenCL wrapper for Intel's unique chip ID function built for the Cyclone V chip on the DE1-SoC board
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May 6, 2019 - C++
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cyclone-v
Here are 57 public repositories matching this topic...
FPGA implementation of the XTEA block cipher in VHDL, targeting Altera DE1-SoC (Cyclone V)
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Feb 20, 2026 - VHDL
Cyclone V SoC ALSA
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Nov 7, 2025 - Verilog
A 16-bit picoComputer implementation on an FPGA.
cpu simulation verilog synthesis vlsi cyclone-v faculty-project vga-controller picocomputer ps2-controller fpga-programming vlsi-design cyclone-iii
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Mar 19, 2026 - Shell
VHDL programming about basic N-bit binary calculator ( + - x / ) for altera fpga cyclone v board
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Nov 27, 2022 - VHDL
Verilog RISC Processor Design
processor-architecture pipeline processor cyclone verilog altera risc hdl verilog-hdl quartus-prime cyclone-iv cyclone-v altera-fpga verilog-project verilog-code
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Jul 8, 2021 - Verilog
DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA
ds1302 systemverilog hdl modelsim quartus-prime cyclone-v rtc-module hardware-description-language altera-fpga terasic-de10-standard
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Jul 30, 2022 - SystemVerilog
A SystemVerilog-based UART (Universal Asynchronous Receiver/Transmitter) module built from scratch using FSM design. Includes baud tick generator, transmitter and receiver FSMs, and simulation testbenches for 8N1 serial communication.
open-source fpga rtl loopback uart altera digital-logic systemverilog hdl serial-communication cyclone-v educational-project intel-quartus hardware-design
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Aug 11, 2025 - SystemVerilog
Waveform generator on DE1-SoC FPGA - sine/PWM waves, 16 frequencies (10Hz-10kHz), TLC7524CN DAC
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Dec 11, 2025 - VHDL
Basic Stopwatch Design using Terasic DE-10 Standard FPGA
systemverilog hdl modelsim quartus-prime cyclone-v hardware-description-language altera-fpga terasic-de10-standard
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Jul 30, 2022 - SystemVerilog
A complete guide to Nios II Hardware Acceleration: From Software implementation to DMA & SIMD optimization. Includes detailed documentation and Cocotb verification environment
fpga simd verilog altera hardware-acceleration dma system-on-chip cyclone-v intel-fpga cocotb nios-ii
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Feb 12, 2026 - C
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