Project for UART and SPI integration into a system for reading and processing an ADS7841 output

A 16-bit picoComputer implementation on an FPGA.

Cyclone V SoC Hard PCIe Root Port

FPGA implementation of the XTEA block cipher in VHDL, targeting Altera DE1-SoC (Cyclone V)

A complete guide to Nios II Hardware Acceleration: From Software implementation to DMA & SIMD optimization. Includes detailed documentation and Cocotb verification environment

[WIP] Modern Amiga 1200 clone implementation using Cyclone V FPGA

Waveform generator on DE1-SoC FPGA - sine/PWM waves, 16 frequencies (10Hz-10kHz), TLC7524CN DAC

Cyclone-V-MIPI-OV13850

Cyclone V MIPI OV4689

Cyclone-V-MIPI-IMX291

C5 MIPI IMX415

Cyclone V SoC ALSA

Cyclone V SoC ALSA MUX

Cyclone V SoC Simple Frame Buffer

Adaptive Thresholding on FPGA (2025A eeic-exp, UTokyo)

Yocto Project BSP meta-layer for Intel (ALTERA) SoC-FPGAs (SoCFPGA) - with step by step guide

A SystemVerilog-based UART (Universal Asynchronous Receiver/Transmitter) module built from scratch using FSM design. Includes baud tick generator, transmitter and receiver FSMs, and simulation testbenches for 8N1 serial communication.

Sobel is a border recognizer CLI application that applies multiples filter algorithms and uses the Laplace MPU for convolution. This project was made for the 3rd PBL of TEC499 - Digital Systems.

Script to build the bootloader (u-boot) and bring all components to a bootable image for Intel (ALTERA) SoC-FPGAs

A collection of Verilog code examples, perfect for beginners or anyone looking to learn Verilog. These examples are based on my homework assignments from my university and include comments and explanations to help you understand the code better. Check out the link below for more information about Verilog!! 👇