Design and implementation of RISC-V processor with a pipelined datapath, controller, and hazard unit.
Sobel is a border recognizer CLI application that applies multiples filter algorithms and uses the Laplace MPU for convolution. This project was made for the 3rd PBL of TEC499 - Digital Systems.
Design and implementation of RISC-V processor with a single-cycle datapath and controller.
👾 My studies with Verilog and notions of digital systems.
Verilog-based vending machine controller IP core, supporting multi-clock domain operation, inventory management, and currency denominations. Built with the APB protocol for efficient configuration, it offers smart change calculation and robust error handling. Developed in the SURE ProEd internship training with experts.
Digital systems class at uni
Proyecto Final: Sistemas digitales avanzados
Uma reprodução simplificada do jogo clássico de arcade asteroids, para sintetização em placa FPGA.
This repo contains Verilog Assignments of the course ES-204 Digital Systems held in II-Semester 2024 at IIT Gandhinagar - Prof. Joycee Mekie
"Verilog HDL implementations of Hadamard and DCT (1D and 2D) transforms with modular design and complete simulations."
🖼️ Implement FPGA image processing modules in Verilog, featuring basics to advanced vision algorithms, all equipped with testbenches for easy validation.
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