Deluxe RISC processor
DLX RISC Processor implementation with extended instruction set and windowed register file
Design and development of a complete RISC CPU with: five stage pipeline, forwarding, automatic hazard detection, BTB using LRU policy replacement, four-cycle hardware multiplier.
Digital design and synthesis of a DLX processor in VHDL
ALU is the core of all operations, it elaborate two operands and performs logical and arithmetic operations based on the instruction passed to it by the CU.
A pipelined DLX processor implemented in VHDL. Includes a 5-stage datapath with hazard and forwarding units, testbenches, a Python single-cycle emulator for fast verification, and a fully automated physical implementation flow.
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