VHDL 2008/93/87 simulator

An abstraction library for interfacing EDA tools

SPI master and SPI slave for FPGA written in VHDL

Simple UART controller for FPGA written in VHDL

Repurposing existing HDL tools to help writing better code

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

A JSON library implemented in VHDL.

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

Scripts to build and use docker images including GHDL

A Python package to use FPGA development tools programmatically.

cryptography ip-cores in vhdl / verilog

Sources for package management systems to build GHDL

Trying to verify Verilog/VHDL designs with formal methods and tools

Virtual development board for HDL design

A tool to invoke ghdl/gtkwave functions, including error highlighting

Collection of generic VHDL modules

Co-simulation and behavioural verification with VHDL, C/C++ and Python/m

✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

Library of reusable VHDL components

Professional VHDL Class Solution - StopWatch