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PyFPGA / symbiflow_cli

A possible replacement for openflow, which would be ideally contributed to the SymbiFlow project

icestorm ghdl yosys nextpnr prjtrellis ghdl-yosys-plugin

Updated Aug 2, 2021
Python

Synthesisable VHDL-2008 cores for Kalyna (DSTU 7624:2014), Strumok (DSTU 8845:2019), Kuznyechik, GOST 28147-89 and RC4 — each with a self-checking testbench validated against published vectors (RFC 7801/8891, DSTU Annex D).

Updated Sep 8, 2026
VHDL

Lucretia / ghdl_whiz

Star

VHDL Whiz tutorial playlist with GHDL

fpga vhdl ghdl fpga-programming

Updated Dec 1, 2025
VHDL

LogiMentor / lm_math_float

Star

LogiMentor floating point VHDL library

fpga math vhdl diamond rtl xilinx vivado altera floating-point ghdl quartus microsemi intel-fpga lattice-fpga libero vhdl-2008 microchip-fpga

Updated Jun 15, 2026
VHDL

ElecGeek / PulsesGene

Star

Fun project to produce (only) pulses as the MultiSignalGene do, with analogue circuits and FPGA or 74HC logic circuits.

hardware electronics vhdl spice ghdl yosys logic-circuit vhdl-code fpga-programming pcb-design

Updated Jan 29, 2026
Gerber Image

tivaliy / ghdl-jenkins-swarm-slave

Star

Docker-based Jenkins swarm slave client with GHDL software

docker-container vhdl jenkins-jobs ci-infrastructure ghdl vunit jenkins-swarm

Updated Apr 4, 2017
Shell

mahdidou711 / vhdl-integer-sqrt

Star

Synthesizable 16-bit integer square-root core in VHDL with exhaustive verification and Terasic DE1 FPGA integration.

fpga vhdl ghdl integer-arithmetic digital-design terasic-de1 cyclone-ii

Updated Sep 12, 2026
VHDL

lrsb / digitallogicdesign-vhdl-2019

Star

A VHDL implementation of a Manhattan distance calculator

vhdl vivado ghdl

Updated Oct 21, 2021
VHDL

JochiSt / icebreaker-VHDL

Star

Some examples using VHDL in combination with the icebreaker board

simulation vhdl ghdl yosys icebreaker ghdl-yosys-plugin cxxrtl

Updated Dec 10, 2024
Makefile

rlangoy / HDLBoard

Star

HDLBoard — Write VHDL and watch it run

simulator fpga vhdl de1-soc ghdl

Updated Sep 20, 2026
TypeScript

LogiMentor / lm_util

Star

Logimentor Utility library

open-source utility fpga hardware simulation vhdl helpers diamond rtl xilinx vivado altera lattice hdl ghdl digital-design quartus

Updated Jul 6, 2026
VHDL

sikienzl / FPGA_Alliance_Scripts

Sponsor

Star

Automation scripts for running and cleaning an Alliance-based VHDL synthesis flow using vasy, boom, boog, and loon.

cli automation fpga vhdl eda python3 ghdl alliance logic-synthesis

Updated Apr 18, 2026
Python

ShreyaNarasimhaKamath / fir-filter-vhdl-

Star

8-tap FIR low-pass filter implemented in VHDL. Verified with impulse, step and noisy sine tests using GHDL simulation.

python fpga signal-processing dsp vhdl ghdl

Updated Apr 25, 2026
VHDL

Feki-Tech / fpga-vhdl-primer

Star

VHDL/FPGA-Einstieg aus Embedded-Linux-Perspektive: 5 Lektionen (DE), RTL-Module mit GHDL-Testbenches in CI

tutorial embedded fpga vhdl ghdl testbench

Updated Jul 15, 2026
VHDL

LogiMentor / lm_memories

Star

lm_memories is an open-source VHDL memory and FIFO library by LogiMentor. The library is released under Apache-2.0 and is intended for both academic and commercial FPGA projects. Commercial support, FPGA integration, vendor-specific validation, and custom memory/FIFO development are available from LogiMentor.

open-source fpga ram hardware simulation memory vhdl diamond rtl xilinx vivado altera lattice fifo hdl ghdl digital-design bram quartus

Updated Jun 17, 2026
VHDL

lla7wel / fpga-ripple-carry-adder

Star

1-bit full adder + 4-bit ripple-carry adder in VHDL — verified on Basys 3 hardware, in Vivado simulation, and exhaustively in CI with self-checking GHDL testbenches

fpga continuous-integration vhdl vivado digital-logic ghdl basys3 self-checking-testbench

Updated Jul 24, 2026
VHDL

syfluqs / hdl_scratchpad

Star

VHDL scratchpad

vhdl ghdl

Updated Feb 18, 2020
VHDL

rohankalbag / superscalar-risc

Star

Course Project - Advanced Computer Architecture - Autumn Semester 2022 - Indian Institute of Technology Bombay

vhdl risc gtkwave ghdl superscalar-cpu

Updated Dec 13, 2022
VHDL

lla7wel / basys3-decoders

Star

VHDL combinational decoders on the Digilent Basys 3 (Artix-7) — exhaustively verified with GHDL, hardware-validated, with full Vivado batch build flow

fpga continuous-integration vhdl digital-logic ghdl basys3

Updated Jul 24, 2026
VHDL

p-nordmann / cocotest

Star

Lightweight, opinionated test orchestration framework for cocotb.

python vhdl verification verilog systemverilog ghdl cocotb cosimulation

Updated Sep 13, 2026
Python

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ghdl

Here are 134 public repositories matching this topic...

PyFPGA / symbiflow_cli

AlexMelanFromRingo / vhdl-rc4

Lucretia / ghdl_whiz

LogiMentor / lm_math_float

ElecGeek / PulsesGene

tivaliy / ghdl-jenkins-swarm-slave

mahdidou711 / vhdl-integer-sqrt

lrsb / digitallogicdesign-vhdl-2019

JochiSt / icebreaker-VHDL

rlangoy / HDLBoard

LogiMentor / lm_util

sikienzl / FPGA_Alliance_Scripts

ShreyaNarasimhaKamath / fir-filter-vhdl-

Feki-Tech / fpga-vhdl-primer

LogiMentor / lm_memories

lla7wel / fpga-ripple-carry-adder

syfluqs / hdl_scratchpad

rohankalbag / superscalar-risc

lla7wel / basys3-decoders

p-nordmann / cocotest

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