HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators

Hashslayer is an open-source demo tool showcasing AWS EC2 F1 FPGA instances' power in cracking hashes. It leverages custom hardware for accelerated cryptographic operations, highlighting innovative FPGA-based performance.

High performance C++ uuid generator

Aureal A3D Software Development Kit

Common code for working with Vitis™ Unified Software Platform in ROS 2.

🛠️ Extract and convert neural network weights from Keras/TensorFlow to optimized binary format, streamlining deployment for embedded systems and custom engines.

Sudoku solver which uses hardware instruction set to speed up significantly the process

A hardware accelerated AES implementation for the Embedded Parallel Operating System from LISHA/UFSC.

Project for the "Symbolic and Evolutionary Artificial Intelligence" class at Pisa University

Hardware Accelerated Ray Tracing using Vulkan

An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs

Neural network weight extractor with batch normalization folding for hardware acceleration (FPGA, ASIC, embedded systems)

An accelerated implementation of the kNN algorithm on the Kria KV260 FPGA

C++ 20 based audio framework

ONNX Runtime: cross-platform, high performance ML inferencing and training accelerator

Vitis High Level Synthesis Introduction

An open source runtime application & templates for DEEPX devices

A really fast, secure random file generator. Much faster than /dev/urandom.

Subdivision surface approximation in real-time using hardware tesselation