OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

IDEA project source files

EDA physical synthesis optimization kit

DATC RDF

A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Verification""

The Verilog source code for DRUM approximate multiplier.

An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization

Benchmarks for Approximate Circuit Synthesis

Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction

This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.

An approximate logic synthesis tool under the maximum error constraint

An application using Cadence IC Package

MATLAB and HDL models of ACA-CSU approximate adders

Highly efficient delay-driven approximate logic synthesis

MS Technical Paper - A study on placement algorithms for heterogeneous FPGAs.

ALMOST: Adversarial Learning to Mitigate Oracle-less ML Logic Locking Attacks via Synthesis Tuning

Extract leaf level RTL modules from OpenROAD and collect PPA numbers generated by Yosys

the Structural Implementation and Logic Synthesis of a Hash Generator System. This project was developed as the Third Assignment of the Computer-Aided Design of Digital Systems (CAD) course at the University of Tehran.

Microprocessor Design using Verilog HDL built and tested in Vivado Design Suite

Logic Synthesis QOR study, the best and worst case for hold and setup