max10

Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components

Intel Quartus Prime Synthesis Engine for Docker

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

Music Light Cube | 音樂全彩光立方（主倉庫）

Simple SoC in VHDL with full toolchain and custom board.

Reference designs and firmware for open-source RISC-V core implementation on MX10 and SpiderSoM

Pong game on FPGA Max 10 DE10-Lite, written in VHDL.

Tutorial and example projects for the Arrow MAX1000 FPGA board

Projects and labs from the courses dictated in https://www.coursera.org/specializations/fpga-design. Projects are sometimes simulated, and implemented in either a MAX10-Lite or an Arrow MAX1000 board.-

Clock Data Recovery | 時鐘數據恢復

NeoPixel LED Controller | NeoPixel LED 控制器 | 基於MAX10 FPGA的音樂全彩光立方LED控制器

Conway's game of life at 1 million FPS

SiFive's Freedom e300 for the DECA Max10 FPGA

Automatically create a NIOS II Eclipse Project with the latest FreeRTOS Version, the Intel hwlib and more...

Zilog Z80 with 8kB ROM and 8kB RAM and Intel 8052 with 12kB ROM and 16kB RAM running BASIC. Intel 8052 runs on BASIC-52 V1.31 with I2C and SFR extensions. Z80 runs on Microsoft BASIC v4.7b with 8kB RAM. Both designs implemented using VHDL and runs at 50MHz using PLL from 12MHz. The board is DIP40 form factor and having onboard USB Blaster.

ADC demo on the Terasic DE10-Lite board with MAX10 FPGA

Tool that removes lines in .svf files to preserve the security key stored in Intel® MAX® 10 devices.

Source codes of examples from the book Verilog by Examples

JH_Advanced Haasoscope

Indicar direcciones correctas para obtener MicroFPGAs CYC1000 MAX1000