An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Specula is a Out-of-Order RISC-V RV32I core featuring basic Dynamic Scheduling and Register Renaming. Designed for simulation (WIP)

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model

Open Source Architecture Code Analyzer

Educational computer simulator on a mission to "superscale" the study of computer architecture fundamentals

Microarchitecture impact analysis using gem5 - Computer Architecture course project - Computer Science @ FAMAF (UNC)

Keyed Watermarks in Apache Flink

A simple superscalar out-of-order RISC-V microprocessor

An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga.

Second Prize in NSCSCC 2024. An out-of-order CPU designed by NoAXI team from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛（龙芯杯）团队赛二等奖作品

try to design a Single_Emission_Out-of-Order_Pipeline_RISC-V_Processor

Advanced Architecture Labs with CVA6

This Verilog implementation represents a 32-bit MIPS processor featuring out-of-order execution.

High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)

Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022

CENOS: The Modern CPU Simulator

Taurus 3001 RISC-V 64-bit Privileged Minimal System Processor for T110/T28 ASIC

Basic Implementation of Tomasulo Algorithm, with memory unit pipelined.

EdgeMailer is a tool that tests rate limits of mail providers, it uses libcurl and libuv to make concomitant assynchronous request. This tool is outdated and now is closed source and belongs to YouSendr.

Go implementation of a bitmap ring-buffer which tracks the state of windowed out-of-order processing over a sequence of logical offsets