An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Open Source Architecture Code Analyzer
A simple superscalar out-of-order RISC-V microprocessor
Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
Advanced Architecture Labs with CVA6
Second Prize in NSCSCC 2024. An out-of-order CPU designed by NoAXI team from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛（龙芯杯）团队赛二等奖作品
A compiler, assembler, and processor.
Educational computer simulator on a mission to "superscale" the study of computer architecture fundamentals
Full superscalar RV32I out-of-order processor with Tomasulos Algorithm, 7-stage pipeline, and UVM testbench. 1st Place + Special Jury Award — SanDisk Hardware Hackathon.
An approach to apply concept drifts and ADWIN on the streams event time to reason about the progress of watermarks
Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022
Taurus 3001 RISC-V 64-bit Privileged Minimal System Processor for T110/T28 ASIC
3D WebGL visualization of a gem5 out-of-order CPU core executing a program — PGSimCity for computer architecture. gem5 tracer patch + React/three.js interactive viewer.
Keyed Watermarks in Apache Flink
try to design a Single_Emission_Out-of-Order_Pipeline_RISC-V_Processor
Introduction in Dynamic Instruction Scheduling (Advanced Computer Architecture) implementing Tomasulo's Algorithm
CENOS: The Modern CPU Simulator
Superscalar OoO RISCV processor written in Chisel
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