This repository presents design of on-chip clock multiplier(8X PLL) using open source EDA tool OSU 180nm technology node

This project implements a bit error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed transmitted signals with received signal and counts up an error counter if their logic levels differ.

Guitar triggered PLL Synth effect

Design of Phase locked loop for 2.4 GHz frequency in 180nm Technology

Train your PLL skills on Rubik's cube with this groovy script

This project provides a simple and well-documented MATLAB implementation of a Phase-Locked Loop (PLL), developed as part of a 5th semester mini project. The final version focuses on clarity, structure, and ease of understanding.

Customizable Keyboard-driven PLL recognition trainer

Firmware (Sketch) for Arduino MEGA DDS (Direct Digital Synthesis) Analog Devices AD9915 Arduino Shield by GRA & AFCH

This project shows the design of a frequency synthesizer PLL system that produces a 1.28 GHz signal with a reference input of 40 MHz.

Design of Phase-Locked-Loop using 45nm technology on Cadence Virtuoso tool

A Simulink Model of Dynamic Mode AFM

ADF4368 register control application

A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier

ESP32 as radio transmitter

Alternative version of the MTS module (https://github.com/TU-Darmstadt-APQ/MTS_module) for 80 MHz and 200 MHz AOMs.

Design and generate the GDSII file for an 8x PLL Clock Multiplier IP with open source PDK & tools

Compute Pseudo-Log-Likelihood (PLL) and PPPL for protein sequences using ESM2 models

TSA5511 PLL Controller for Arduino

SAA1057 on 2-meter band

Data and code to design and evaluate the PLL-based true random number generator according to the paper "Enhancing Quality and Security of the PLL-TRNG" (published and awarded at TCHES 2023).