SAA1057 Stereo PLL Controller

Design of Phase locked loop for 2.4 GHz frequency in 180nm Technology

Guitar triggered PLL Synth effect

Firmware (Sketch) for Arduino MEGA DDS (Direct Digital Synthesis) Analog Devices AD9915 Arduino Shield by GRA & AFCH

Compute Pseudo-Log-Likelihood (PLL) and PPPL for protein sequences using ESM2 models

Alternative version of the MTS module (https://github.com/TU-Darmstadt-APQ/MTS_module) for 80 MHz and 200 MHz AOMs.

Generating PLL configuration parameters

ADF4368 register control application

A repository of the recently published PLLs performance.

Library for ICS501.

tsa5511/12 fm pll

Charge Pump PLL Modeling and Simulation. A block diagram level simulator for Capsim was written in C which allows for very fast simulations and the verification of PLL performance. The objective is to match the nonlinear mixed analog/digital PLL circuit performance with high level fast "C" modeling of the charge pump PLL.

23cm NBFM transceiver

Customizable Keyboard-driven PLL recognition trainer

Xilinx Artix-7 FPGA design using block ram, XADC and a SPI slave (SCARF). The block ram is dual port and can be written by either SPI or XADC samples, and only read by SPI.

Design of Phase-Locked-Loop using 45nm technology on Cadence Virtuoso tool

A Simulink Model of Dynamic Mode AFM

This project provides a simple and well-documented MATLAB implementation of a Phase-Locked Loop (PLL), developed as part of a 5th semester mini project. The final version focuses on clarity, structure, and ease of understanding.

Bash scipt for loading AD9547/AD9548 configuration (.stp) via I2C