Verilog Implementation of an ARM LEGv8 CPU

LEGv8 CPU implementation and some tools like a LEGv8 assembler

VHDL implementation of a 1 Hz single cycle CPU that supports recursive function calls

Single Cycle 32 bit MIPS

Microprocessor without Interlocked Pipelined Stages (MIPS) architectures implemented in single-cycle and multi-cycle formats.

implement single cycle TOY processor with verilog

An implementation of rv32i single cycle processor on logisim

MIPS CPU constructed in verilog

Single-cycle waveform generator

Final Year - Hardware Realisation of a Computer System (3002CEM) Project

1052_計算機組織 COMPUTER ORGANIZATION

Repository regarding the Practical Works of the Computer Organization discipline

An implementation of Mips processor - My Computer Architecture course final project

Verilog modules covering the single cycle processor

This is a project currently doing under the module EN3021 Digital System Design, Semester 5, Department of Electronic & Telecommunication Engineering, University of Moratuwa, Sri Lanka.

A very simple implementation of a single cycle ARM CPU with a fairly reduced instruction set.

This project involves the design, simulation, and implementation of a 16-bit Microprocessor based on a custom Simple Instruction Set Architecture (ISA). The core objective was to implement and compare two different CPU architectures (Single Cycle & Pipeline) to optimize processing performance.

Single-cycle and multi-cycle implementation of a subset of MIPS instruction set

MIPS processor designed in Verilog.

C++ simulation of a single-cycle LEGv8 processor. Replicating datapath control, memory operations, branching, and instruction execution.