#

single-cycle

Here are 36 public repositories matching this topic...

salsdsp / 1903_WAVE

Single-cycle waveform generator

waveform cycle single single-cycle waveform-generator single-cycle-waveform

Updated Feb 7, 2026
Python

NguyenDinhNhatNguyen / 16-bit-Simple-ISA-Microprocessor-Design

This project involves the design, simulation, and implementation of a 16-bit Microprocessor based on a custom Simple Instruction Set Architecture (ISA). The core objective was to implement and compare two different CPU architectures (Single Cycle & Pipeline) to optimize processing performance.

pipeline isa modelsim verilog-hdl quartus-prime single-cycle teamwork-project blockdiagrams cpu16bit

Updated Feb 1, 2026
HTML

MotasimAbid19 / 22-bit-mips-datapath-logisim

Logisim implementation of a custom 22-bit MIPS-like single-cycle datapath with control unit and a Python assembler that outputs Logisim ROM images.

python cpu mips assembler isa rom datapath digital-logic computer-architecture alu logisim microarchitecture single-cycle control-unit register-file verilog-architecture

Updated Jan 6, 2026
Python

cnily03-hive / single-cycle-cpu

Single-Cycle CPU for Homework of Computer System Design in CUMT.

cpu verilog verilog-hdl single-cycle

Updated Dec 25, 2025
Verilog

GrahamPellegrini / Legv8-Single-Cycle-Sim

C++ simulation of a single-cycle LEGv8 processor. Replicating datapath control, memory operations, branching, and instruction execution.

processor assembly single-cycle cpu-architecture legv8 instruction-simulation

Updated Jul 22, 2025
Awk

Single_Cycle_CPU_Core

riccardoserraino / Single_Cycle_CPU_Core

Design of a single cycle CPU based on 36 instructions of RISCV architecture.

cpu riscv verilog hdl verilog-hdl single-cycle riscv32 single-cycle-processor

Updated Mar 23, 2025
Verilog

jack74387 / Single-Cycle-8-bit-CPU

Single-Cycle 8-bit CPU designed for basic instruction execution with Logisim.

cpu single-cycle circuit-design computer-organization-and-design

Updated Feb 9, 2025

muhammadtalhasami / rv32I_single_cycle_logisim

An implementation of rv32i single cycle processor on logisim

hardware rtl assembly-language microprocessor hardware-designs logisim rv32i single-cycle single-cycle-processor rv32i-processor rsic-v

Updated Apr 12, 2024

namiwijeuom / 32-Bit-Non-Pipelined-Single-Cycle-Processor

This is a project currently doing under the module EN3021 Digital System Design, Semester 5, Department of Electronic & Telecommunication Engineering, University of Moratuwa, Sri Lanka.

processor single-cycle processor-design singlecycle-processor

Updated Dec 29, 2023
SystemVerilog

FUM-Computer-Architecture-Single-Cycle-MIPS-Processor

JavidChaji / FUM-Computer-Architecture-Single-Cycle-MIPS-Processor

Single Cycle MIPS Processor implementation, Computer Assignment for Computer Architecture course in Ferdowsi University of Mashhad

mips processor verilog computer-architecture mips-architecture mips-processor single-cycle fum single-cycle-processor ferdowsi-university-of-mashhad

Updated Nov 17, 2023
Verilog

frottori / VHDL_MIPS_Project

Undergraduate

mips-architecture mips-processor 32bit single-cycle

Updated Nov 15, 2023
VHDL

alumpish / CA-Course-Projects

Projects of the computer architecture course (Fall01) at the University of Tehran.

mips computer-architecture single-cycle multi-cycle booth-multiplier

Updated Oct 6, 2023
Verilog

alighanbari2002 / MIPS-Processor

MIPS processor designed in Verilog.

c mips mips-assembly verilog mips-architecture single-cycle multi-cycle single-cycle-processor multi-cycle-processor

Updated Aug 18, 2023
Verilog

alighanbari2002 / Computer-Architecture-Course-Projects

Verilog descriptions of MIPS single-cycle, multi-cycle & booth multiplier.

mips mips-assembly verilog computer-architecture mips-architecture single-cycle multi-cycle booth-multiplier single-cycle-processor multi-cycle-processor

Updated Aug 18, 2023
Verilog

TahaTabatabaei / mips-verilog

Single-cycle and multi-cycle verilog implementation of a subset of MIPS instruction set

mips verilog mips-architecture single-cycle multi-cycle

Updated Jul 26, 2023
Verilog

SheidaAbedpour / Single-Cycle-Datapath

simple mips architecture

assembler verilog computer-architecture logisim mips-architecture single-cycle data-path

Updated Jul 18, 2023
Verilog

TCL606 / MIPS_CPU

MIPS CPU constructed in verilog

cpu mips single-cycle multi-cycle

Updated Feb 15, 2023
Verilog

ILoveBacteria / CA-project-mips

An implementation of Mips processor - My Computer Architecture course final project

processor-architecture mips datapath single-cycle

Updated Jan 26, 2023
SystemVerilog

ndyashas / Salaga-RV

Simple RISC-V CPUs running a baremental ray-tracer program.

cpu riscv verilog risc-v baremetal rv32i verilator single-cycle cpu-simulation 5-stage-pipeline jala baremetal-programming eka 5-stages-pipeline

Updated Jan 13, 2023
Verilog

martinKindall / mips_cpu

Single Cycle 32 bit MIPS

fpga mips systemverilog basys3 mips-cpu single-cycle basys3-fpga single-cycle-processor

Updated Dec 24, 2022
SystemVerilog

Improve this page

Add a description, image, and links to the single-cycle topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the single-cycle topic, visit your repo's landing page and select "manage topics."