An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

RISC-V Instruction Set Manual

Hot Reconfiguration Technology demo

Greyhound on IHP SG13G2 0.13 μm BiCMOS process

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU G…

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.