meson s4 for ci - #1039
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sean-anderson-brivo wants to merge 15 commits into
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meson s4 for ci#1039sean-anderson-brivo wants to merge 15 commits into
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Add support for amlogic s4 (S805X2/S905W2/S905Y4) SoCs. These are very similar to other recent SoCs, with the exception of a workaround for some BL2 (mis)behavior. Signed-off-by: Sean Anderson <sanderson@brivo.com> Patch-cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Instead of passing a struct clk (containing the device and an unrelated id) and a separate id parameter to most functions, just pass a single struct clk with the correct id. This is in preparation for converting some instances of meson_clk_* functions to clk_* functions to allow for greater extensibility. In general, this transformation requires constructing a synthetic struct clk wherever we used to call a function with an id different from clk->id. We don't bother to call clk_request since we don't implement it ourselves. Signed-off-by: Sean Anderson <sanderson@brivo.com> Patch-cc: Lukasz Majewski <lukma@denx.de>
This function is useful for other drivers, but it's tied to the a1's meson_mux_set_rate implementation. Convert it to use clk_set_rate so the drivers's set_rate implementation will be used (no matter what it is). Signed-off-by: Sean Anderson <sanderson@brivo.com> Patch-cc: Lukasz Majewski <lukma@denx.de>
In preparation for moving a1 versions of several common functions into a shared file, rename all the conflicting functions to have a soc-specific component. Signed-off-by: Sean Anderson <sanderson@brivo.com> Patch-cc: Lukasz Majewski <lukma@denx.de>
Export several useful functions from a1 to a common file. These will be used for s4 support. Signed-off-by: Sean Anderson <sanderson@brivo.com> Patch-cc: Lukasz Majewski <lukma@denx.de>
One of the s4 clocks has a non-integer divisor (2.5). Add support for this. Signed-off-by: Sean Anderson <sanderson@brivo.com> Patch-cc: Lukasz Majewski <lukma@denx.de>
Several s4 clocks use power-of-two dividers. Add support for them. Signed-off-by: Sean Anderson <sanderson@brivo.com> Patch-cc: Lukasz Majewski <lukma@denx.de>
Add a clock driver to support for the "s4" series of SoCs (S805X2 and
S905Y4). I've added most of the clocks necessary at boot, although a few
of the unused parents (VID_PLL, RTC) have been omitted. I also left out
the parents of the MPLL clocks, as they have a custom divider. MPLL2 is
enabled by the Ethernet driver but is never actually selected so it's OK
to stub out the parent.
=> clk dump
Rate Usecnt Name
------------------------------------------
24000000 0 |-- xtal-clk
34700000 0 |-- bt-txco
meson-clk-s4 clock-controller@0:
clock-controller@0:
----------------------------------------------------------------------
clk frequency parent state
----------------------------------------------------------------------
sysclk_b_sel 498000000 fclk_div4 N/A
sysclk_b_div 166000000 sysclk_b_sel N/A
sysclk_b 166000000 sysclk_b_div enabled
sysclk_a_sel 24000000 xtal N/A
sysclk_a_div 24000000 sysclk_a_sel N/A
sysclk_a 24000000 sysclk_a_div enabled
sys 166000000 sysclk_b N/A
sd_emmc_c_sel 24000000 xtal N/A
sd_emmc_c_div 24000000 sd_emmc_c_sel N/A
sd_emmc_c 24000000 sd_emmc_c_div enabled
sd_emmc_a_sel 24000000 xtal N/A
sd_emmc_a_div 24000000 sd_emmc_a_sel N/A
sd_emmc_a 24000000 sd_emmc_a_div enabled
sd_emmc_b_sel 24000000 xtal N/A
sd_emmc_b_div 24000000 sd_emmc_b_sel N/A
sd_emmc_b 24000000 sd_emmc_b_div enabled
pwm_a_sel 24000000 xtal N/A
pwm_a_div 24000000 pwm_a_sel N/A
pwm_a 24000000 pwm_a_div disabled
pwm_b_sel 24000000 xtal N/A
pwm_b_div 24000000 pwm_b_sel N/A
pwm_b 24000000 pwm_b_div disabled
pwm_c_sel 24000000 xtal N/A
pwm_c_div 24000000 pwm_c_sel N/A
pwm_c 24000000 pwm_c_div disabled
pwm_d_sel 24000000 xtal N/A
pwm_d_div 24000000 pwm_d_sel N/A
pwm_d 24000000 pwm_d_div disabled
pwm_e_sel 24000000 xtal N/A
pwm_e_div 24000000 pwm_e_sel N/A
pwm_e 24000000 pwm_e_div disabled
pwm_f_sel 24000000 xtal N/A
pwm_f_div 24000000 pwm_f_sel N/A
pwm_f 24000000 pwm_f_div disabled
pwm_g_sel 24000000 xtal N/A
pwm_g_div 24000000 pwm_g_sel N/A
pwm_g 24000000 pwm_g_div disabled
pwm_h_sel 24000000 xtal N/A
pwm_h_div 24000000 pwm_h_sel N/A
pwm_h 24000000 pwm_h_div enabled
pwm_i_sel 24000000 xtal N/A
pwm_i_div 24000000 pwm_i_sel N/A
pwm_i 24000000 pwm_i_div disabled
pwm_j_sel 24000000 xtal N/A
pwm_j_div 24000000 pwm_j_sel N/A
pwm_j 24000000 pwm_j_div enabled
ethphy 166000000 sys enabled
sdemmc_a 166000000 sys enabled
sdemmc_b 166000000 sys enabled
nand 166000000 sys enabled
eth 166000000 sys enabled
uart_a 166000000 sys enabled
uart_b 166000000 sys enabled
uart_c 166000000 sys enabled
uart_d 166000000 sys enabled
uart_e 166000000 sys enabled
usb 166000000 sys enabled
i2c_m_a 166000000 sys enabled
i2c_m_b 166000000 sys enabled
i2c_m_c 166000000 sys enabled
i2c_m_d 166000000 sys enabled
i2c_m_e 166000000 sys enabled
usb1_to_ddr 166000000 sys enabled
pwm_ab 166000000 sys enabled
pwm_cd 166000000 sys enabled
pwm_ef 166000000 sys enabled
pwm_gh 166000000 sys enabled
pwm_ij 166000000 sys enabled
xtal 24000000 unknown N/A
fclk_div2 996000000 unknown N/A
fclk_div2p5 796800000 unknown N/A
fclk_div3 664000000 unknown N/A
fclk_div4 498000000 unknown N/A
fclk_div5 398400000 unknown N/A
fclk_div7 284571428 unknown N/A
hifi_pll 1176000000 unknown N/A
gp0_pll unknown unknown N/A
mpll0 unknown unknown N/A
mpll1 unknown unknown N/A
mpll2 unknown unknown N/A
mpll3 unknown unknown N/A
hdmi_pll unknown unknown N/A
meson-clk-s4 clock-controller@8000:
clock-controller@8000:
----------------------------------------------------------------------
clk frequency parent state
----------------------------------------------------------------------
fixed_pll_dco 3984000000 xtal N/A
fixed_pll 1992000000 fixed_pll_dco N/A
fclk_div2_div 996000000 fixed_pll N/A
fclk_div2 996000000 fclk_div2_div enabled
fclk_div3_div 664000000 fixed_pll N/A
fclk_div3 664000000 fclk_div3_div enabled
fclk_div4_div 498000000 fixed_pll N/A
fclk_div4 498000000 fclk_div4_div enabled
fclk_div5_div 398400000 fixed_pll N/A
fclk_div5 398400000 fclk_div5_div enabled
fclk_div7_div 284571428 fixed_pll N/A
fclk_div7 284571428 fclk_div7_div enabled
fclk_div2p5_div 796800000 fixed_pll N/A
fclk_div2p5 796800000 fclk_div2p5_div enabled
gp0_pll_dco unknown xtal N/A
gp0_pll unknown gp0_pll_dco N/A
hifi_pll_dco 4704000000 xtal N/A
hifi_pll 1176000000 hifi_pll_dco N/A
hdmi_pll_dco unknown xtal N/A
hdmi_pll_od unknown hdmi_pll_dco N/A
hdmi_pll unknown hdmi_pll_od N/A
mpll_50m_div 49800000 fixed_pll_dco N/A
mpll_50m 49800000 mpll_50m_div N/A
mpll0 unknown unknown disabled
mpll1 unknown unknown disabled
mpll2 unknown unknown enabled
mpll3 unknown unknown disabled
xtal 24000000 unknown N/A
Signed-off-by: Sean Anderson <sanderson@brivo.com>
Patch-cc: Lukasz Majewski <lukma@denx.de>
Parse devicetree properties so things like max-frequency are respected. Upstream-Status: Pending Signed-off-by: Sean Anderson <sanderson@brivo.com> Patch-cc: Peng Fan <peng.fan@nxp.com> Patch-cc: Jaehoon Chung <jh80.chung@samsung.com>
On newer SoCs, the drivestrength registers are included with the rest of the GPIO registers. Linux has a rather complex system that uses a helper function to fix up the registers for each SoC. Instead of that, just default to the gpio registers if the ds register are absent, like we do for pull/pull-enable. This silences warnings like meson-s4-pinctrl pinctrl@4000: drive-strength-microamp not supported while booting on s4. Signed-off-by: Sean Anderson <sanderson@brivo.com>
Add pinctrl support for the s4. This is a direct adaptation of Linux
commit 775214d389c25 ("pinctrl: meson: add pinctrl driver support for
Meson-S4 Soc") with fixes through 7.2.
=> pinmux status -a
--------------------------
pinctrl@4000:
GPIOE_0 : emmc_nand_d0 (1)
GPIOE_1 : emmc_nand_d1 (1)
GPIOB_0 : emmc_nand_d2 (1)
GPIOB_1 : emmc_nand_d3 (1)
GPIOB_2 : emmc_nand_d4 (1)
GPIOB_3 : emmc_nand_d5 (1)
GPIOB_4 : emmc_nand_d6 (1)
GPIOB_5 : emmc_nand_d7 (1)
GPIOB_6 : emmc_clk (1)
GPIOB_7 : GPIOB_9 (0)
GPIOB_8 : emmc_cmd (1)
GPIOB_9 : emmc_nand_ds (1)
GPIOB_10 : nand_ce0 (2)
GPIOB_11 : spif_cs (3)
GPIOB_12 : sdcard_d0_c (1)
GPIOB_13 : sdcard_d1_c (1)
GPIOC_0 : sdcard_d2_c (1)
GPIOC_1 : sdcard_d3_c (1)
GPIOC_2 : sdcard_clk_c (1)
GPIOC_3 : sdcard_cmd_c (1)
GPIOC_4 : GPIOC_6 (0)
GPIOC_5 : GPIOC_7 (0)
GPIOC_6 : pwm_h (3)
GPIOC_7 : pwm_j (3)
GPIOD_0 : uart_b_tx_d (1)
GPIOD_1 : uart_b_rx_d (1)
GPIOD_2 : GPIOD_2 (0)
GPIOD_3 : GPIOD_3 (0)
GPIOD_4 : GPIOD_4 (0)
GPIOD_5 : GPIOD_5 (0)
GPIOD_6 : jtag_1_clk (1)
GPIOD_7 : jtag_1_tms (1)
GPIOD_8 : jtag_1_tdi (1)
GPIOD_9 : jtag_1_tdo (1)
GPIOD_10 : GPIOD_10 (0)
GPIOD_11 : GPIOD_11 (0)
GPIOH_0 : GPIOH_0 (0)
GPIOH_1 : GPIOH_1 (0)
GPIOH_2 : GPIOH_2 (0)
GPIOH_3 : GPIOH_3 (0)
GPIOH_4 : GPIOH_4 (0)
GPIOH_5 : GPIOH_5 (0)
GPIOH_6 : GPIOH_6 (0)
GPIOH_7 : GPIOH_7 (0)
GPIOH_8 : GPIOH_8 (0)
GPIOH_9 : GPIOH_9 (0)
GPIOH_10 : eth_link_led (1)
GPIOH_11 : eth_act_led (1)
GPIOX_0 : sdio_d0 (1)
GPIOX_1 : sdio_d1 (1)
GPIOX_2 : sdio_d2 (1)
GPIOX_3 : sdio_d3 (1)
GPIOX_4 : sdio_clk (1)
GPIOX_5 : sdio_cmd (1)
GPIOX_6 : GPIOX_6 (0)
GPIOX_7 : GPIOX_7 (0)
GPIOX_8 : GPIOX_8 (0)
GPIOX_9 : GPIOX_9 (0)
GPIOX_10 : GPIOX_10 (0)
GPIOX_11 : GPIOX_11 (0)
GPIOX_12 : GPIOX_12 (0)
GPIOX_13 : GPIOX_13 (0)
GPIOX_14 : GPIOX_14 (0)
GPIOX_15 : GPIOX_15 (0)
GPIOX_16 : GPIOX_16 (0)
GPIOX_17 : GPIOX_17 (0)
GPIOX_18 : GPIOX_18 (0)
GPIOX_19 : GPIOX_19 (0)
GPIOZ_0 : GPIOZ_0 (0)
GPIOZ_1 : GPIOZ_1 (0)
GPIOZ_2 : GPIOZ_2 (0)
GPIOZ_3 : GPIOZ_3 (0)
GPIOZ_4 : GPIOZ_4 (0)
GPIOZ_5 : GPIOZ_5 (0)
GPIOZ_6 : GPIOZ_6 (0)
GPIOZ_7 : GPIOZ_7 (0)
GPIOZ_8 : GPIOZ_8 (0)
GPIOZ_9 : GPIOZ_9 (0)
GPIOZ_10 : GPIOZ_10 (0)
GPIOZ_11 : GPIOZ_11 (0)
GPIOZ_12 : GPIOZ_12 (0)
GPIO_TEST : GPIO_TEST_N (0)
Signed-off-by: Sean Anderson <sanderson@brivo.com>
Add s4 support. There are no new features, so just define the layout info. Signed-off-by: Sean Anderson <sanderson@brivo.com>
No new features, just a different compatible. Signed-off-by: Sean Anderson <sanderson@brivo.com>
These SoCs have an almost identical watchdog to other meson SoCs, except
the reset bit has moved. Add a new compatible and driver data.
This commit is based off of Linux commits 55908e388b5da ("watchdog: Add
a new struct for Amlogic-GXBB driver") and 8c776a0401f1d ("watchdog: Add
support for Amlogic-T7 SoCs")
Signed-off-by: Sean Anderson <sanderson@brivo.com>
Patch-cc: Stefan Roese <stefan.roese@mailbox.org>
This adds basic support for the Khadas VIM1S [1]. I built this config on a custom board, and I don't even own a vim1s. Please test! [1] https://www.khadas.com/vim1s Signed-off-by: Sean Anderson <sanderson@brivo.com>
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chewitt
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Aug 18, 2026
| F: board/amlogic/q200/ | ||
| F: include/configs/q200.h | ||
| F: configs/beelink-gt1-ultimate_defconfig | ||
| F: configs/khadas-vim1s_defconfig |
Contributor
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This file is used for GXM compatible devices (S912 and S905D) - You need to create board/amlogic/s4 or similar to track items for the S4 platform.
chewitt
reviewed
Aug 18, 2026
| @@ -0,0 +1,80 @@ | |||
| CONFIG_ARM=y | |||
| CONFIG_SYS_BOARD="q200" | |||
Contributor
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The q200 reference is (again) for GXM so needs to be s4 to align with an s4.h board file under board/amlogic/s4 structure or similar.
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From what I can tell, the q200 board file just sets up the MAC address. I'm not actually sure how this is supposed to work on s4 (at least from what I can tell the mac address is part of the dwmac IP).
Maybe odroid-go-ultra is a better base, since it really doesn't do anything.
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