ddr: altera: iossm: wait for mailbox ready before commands - #1030

io96b_mb_init() starts issuing IOSSM mailbox accesses (mailbox header,
memory interface info, etc.) without first confirming that the IOSSM
firmware has finished initializing its mailbox. If the mailbox is not
yet ready, those accesses operate on an uninitialized interface and can
return bogus data or hang with no useful diagnostic.

The MAILBOX_HEADER register exposes an MB_READY bit (bit 31) that the
IOSSM firmware sets once the mailbox is initialized and ready to accept
commands. When enabled, poll this bit for every assigned IO96B instance
before any mailbox traffic, with a 6s timeout, and hang with a clear
message if it never becomes ready.

Some IOSSM firmware revisions never assert MB_READY, so an unconditional
wait times out and hangs DDR init. Gate the poll behind
CONFIG_IO96B_MB_READY (default n). Enable only when the IOSSM firmware
sets MB_READY.

In the normal boot flow with compatible firmware the check is
effectively free: io96b_mb_init() runs after init_mem_cal(), by which
point the firmware is already up and MB_READY is observed set on the
first read (0 msec). The poll only adds value as a guard against a
missing or wedged mailbox.

Tested-on: SoCFPGA Agilex5 & Agilex7m SoCDK hardware.

Signed-off-by: Chen Huei Lok <chen.huei.lok@altera.com>