arm: dts: socfpga: Add Agilex5 E-Series 013B SoCDK variant - #1046
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Add device tree, U-Boot dtsi and a defconfig for the Agilex5 E-Series
013B SoCDK (DK-A5E013BM16AEA). The board uses a 64 MB QSPI flash with
a different layout than the base SoCDK, so it needs its own DT and
defconfig rather than a DT overlay on the existing target.
Keep Linux-facing MMC essentials in the .dts and Cadence PHY timing in
the U-Boot dtsi, matching the base Agilex5 SoCDK split. Advertise
sd-uhs-sdr50 with 1.8 V signalling (sd_io_1v8_reg); leave SDR104 and
DDR50 to a separate UHS PHY timing series. Alias ethernet0 to the
enabled gmac2 port and use snps,dwxgmac-mdio for its MDIO child.
Guard the &binman { /delete-node/ kernel; } cleanup with CONFIG_FIT so
non-FIT SoCFPGA defconfigs that compile every socfpga_*.dtb continue
to build.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
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Summary
Add device tree, U-Boot dtsi and a defconfig for the Agilex5 E-Series 013B SoCDK (DK-A5E013BM16AEA). The board uses a 64 MB QSPI flash with a different layout than the base SoCDK, so it needs its own DT and defconfig rather than a DT overlay on the existing target.
Changes in v2
&binman { /delete-node/ kernel; }cleanup with CONFIG_FIT so non-FIT SoCFPGA defconfigs that compile every socfpga_*.dtb continue to buildLink: https://lore.kernel.org/all/20260625165909.32177-1-dinesh.maniyam@altera.com/
Test plan
make socfpga_agilex5_013b_defconfig && makesocfpga_agilex5_socdk_013b.dtb