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upadhyepratiiksha-dot/README.md

Hi, I'm Pratiksha Upadhye 👋

Final-year ECE Student | Aspiring RTL Design & Verification Engineer

🔧 About Me

  • 🎓 B.Tech in Electronics & Telecommunication Engineering, RIT Islampur
  • 💡 Hands-on experience designing hierarchical RTL modules (ALU, FSM, UART, memory) verified through testbenches in Xilinx Vivado
  • 🚀 Also bring hardware integration experience from sounding rocket payload development (ESP32, I²C/SPI/UART, GPS/GSM)
  • 📌 Currently focused on strengthening my RTL design & verification fundamentals for VLSI roles

🛠️ Skills & Tools

RTL / VLSI Verilog HDL · FSM Design · Hierarchical Module Design · Testbench Verification · Xilinx Vivado · Quartus · ModelSim

Embedded Systems ESP32 · Arduino · Embedded C · I²C · SPI · UART · GPS/GSM Integration

Programming Verilog · Embedded C · Python (basic)

📂 Featured Verilog / RTL Projects

Project Description
16-bit ALU Hierarchical 16-bit ALU — adder, comparator, logic unit, incrementer/decrementer
UART Transceiver Full-duplex UART with baud generator and 16x-oversampling receiver FSM
Booth Multiplier Signed multiplication using Booth's algorithm — FSM + datapath design
Memory Design (RAM/ROM) Synchronous RAM, asynchronous RAM, and ROM with verification testbenches
FSM Sequence Detector Mealy/Moore FSM detecting a binary sequence, overlapping & non-overlapping modes
Traffic Light Controller FSM-based 4-way traffic signal controller with full state-transition verification

📫 Connect with Me

LinkedIn Email

Popular repositories Loading

  1. verilog-4bit-magnitude-comparator verilog-4bit-magnitude-comparator Public

    4-bit Magnitude Comparator designed using Verilog HDL with hierarchical design and testbench.

    Verilog

  2. Verilog-16bit-ALU Verilog-16bit-ALU Public

    Designed and implemented a 16-bit Arithmetic Logic Unit (ALU) in Verilog HDL using hierarchical RTL design. The project integrates reusable modules such as ripple carry adder, comparator, logic uni…

    Verilog

  3. verilog-sequence-detector verilog-sequence-detector Public

    Designed a sequence detector in Verilog HDL using a Finite State Machine (FSM) to detect a predefined binary sequence. The project demonstrates state transition design, overlapping/non-overlapping …

    Verilog

  4. verilog-traffic-signal-controller verilog-traffic-signal-controller Public

    RTL implementation of a Traffic Light Controller in Verilog HDL using a Finite State Machine (FSM), verified through simulation using a dedicated testbench.

    Verilog

  5. verilog-uart-transceiver verilog-uart-transceiver Public

    Designed a full-duplex UART transceiver in Verilog HDL with a configurable baud-rate generator, 8-bit transmitter, and 16x-oversampling receiver FSM, verified through dedicated Verilog testbenches.

    Verilog

  6. verilog-memory-design verilog-memory-design Public

    Implemented and verified synchronous RAM, asynchronous RAM, and ROM modules in Verilog HDL, covering core memory read/write behavior and timing, each validated with a dedicated testbench.

    Verilog