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OpenTitan: Open source silicon root of trust

SystemVerilog 3,272 979 Updated Apr 3, 2026

The multi-core cluster of a PULP system.

SystemVerilog 113 35 Updated Mar 28, 2026

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SystemVerilog 1,824 709 Updated Feb 17, 2026

pulp_soc is the core building component of PULP based SoCs

Python 83 90 Updated Mar 10, 2025

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

SystemVerilog 546 127 Updated Nov 26, 2024

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

SystemVerilog 974 334 Updated Nov 15, 2024

CocoAlma is an execution-aware tool for formal verification of masked implementations

Python 24 13 Updated Sep 26, 2024

Yet Another Nand Dumper

Python 23 4 Updated Sep 7, 2023

Low-level NAND Flash dump and parsing utility

Python 315 101 Updated Mar 17, 2022

⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform

SystemVerilog 50 16 Updated Jan 6, 2022

⛔ DEPRECATED ⛔ HERO Software Development Kit

Shell 20 7 Updated Jan 6, 2022

REBECCA is a tool for the formal verification of masked cryptographic hardware implementations that, given the netlist of a masked hardware circuit, determines if a correct separation between share…

Verilog 5 2 Updated Feb 23, 2021