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CocoAlma is an execution-aware tool for formal verification of masked implementations

Python 23 12 Updated Sep 26, 2024

REBECCA is a tool for the formal verification of masked cryptographic hardware implementations that, given the netlist of a masked hardware circuit, determines if a correct separation between share…

Verilog 5 2 Updated Feb 23, 2021

The multi-core cluster of a PULP system.

SystemVerilog 109 32 Updated Oct 31, 2025

pulp_soc is the core building component of PULP based SoCs

Python 81 88 Updated Mar 10, 2025

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

SystemVerilog 531 124 Updated Nov 26, 2024

Yet Another Nand Dumper

Python 23 4 Updated Sep 7, 2023

Low-level NAND Flash dump and parsing utility

Python 309 101 Updated Mar 17, 2022

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

SystemVerilog 947 326 Updated Nov 15, 2024

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SystemVerilog 1,705 672 Updated Dec 19, 2025

OpenTitan: Open source silicon root of trust

SystemVerilog 3,064 925 Updated Dec 20, 2025

⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform

SystemVerilog 50 16 Updated Jan 6, 2022

⛔ DEPRECATED ⛔ HERO Software Development Kit

Shell 21 7 Updated Jan 6, 2022