Open source FPGA-based NIC and platform for in-network compute

HDL libraries and projects

Verilog UART

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Universal Memory Interface (UMI)

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

Open source FPGA-based NIC and platform for in-network compute

XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.

"High density, low leakage" digital standard cells for SKY130 provided by SkyWater.

HDL libraries and projects

PlutoSDR HDL libraries and projects

Small footprint and configurable PCIe core

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip …

Pseudo-quantum CPU in Verilog

An open source CPU design and verification platform for academia

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip …