CMOS Inverter
VDD It consists of an enhancement-
type nMOS transistor and an
enhancement type pMOS
transistor.
Push-pull arrangement
Vin
Vout -for high input, nMOS pulls
down the output node while
CL pMOS acts as load
-for low input pMOS pulls up
the output node while the nMOS
acts as the load.
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From the circuit
VGS, n = Vin
V DS,n = Vout
V SG,p = ( VDD- Vin)
V SD,p = (VDD- Vout)
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VDD VDD
Rp
Vout
Vout
Rn
Vin VDD Vin 0
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I Dn
Vin = 0 Vin = 2.5
PMOS Vin = 0.5 Vin = 2 NMOS
Vin = 1 Vin = 1.5
Vin = 1.5 Vin = 1
Vin = 1.5 Vin = 1
Vin = 2 Vin = 0.5
Vin = 2.5 Vin = 0
Vout
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nMOS acts in saturation if
Vin > V TO, n and
V DS, n >= V GS,n – V TO,n >= V in – V TO,n
pMOS acts in saturation if
Vin < ( VDD + V TO, p) and
V DS, p < = V GS, p – V TO, p < = V in– V TO, p
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When the input voltage is smaller than the nMOS threshold
voltage i.e., when Vin < V TO, n
nMOS cut-off and pMOS on operates in linear region
I D,n = I D,p = 0
Drain to source voltage of pMOS also = 0
Vout = VOH = VDD.
When the input voltage exceeds ( VDD + V TO, p) , pMOS turned
off. nMOS in linear region. V DS, n = 0
Vout = VOL = 0
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Region Vin Vout nMOS pMOS
A <V TO,n VOH cut-off linear
B VIL VOH saturation linear
C Vth Vth saturation saturation
D VIH VOL linear saturation
E >(VDD+V TO,p) VOL linear cut-off
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VIL:
For Vin = VIL dVout/ dVin = -1
nMOS in saturation and pMOS in linear region.
kn/2 [ (VGS,n- V TO,n)2] = (kp/2) [ 2(VGS,p- V TO,p) VDS,p – V2DS,p]
kn/2 [ (Vin- V TO,n)2] = (kp/2) [ 2(V in- VDD-V TO,p) ( Vout – VDD) –
( Vout – VDD)2 ]
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Differentiating both the sides w.r.t Vin
kn [ (Vin- V TO,n)] = (kp/) [ (V in- VDD-V TO,p) dVout/dVin+
( Vout – VDD) – ( Vout – VDD) dVout/dVin ]
Substituting Vin = VIL and dVout/dVin = -1, we obtain
VIL = ( 2Vout + V TO,p – VDD + kR.V TO.n)/1+kR
Where kR = kn/kp
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VIH:
nMOS in linear and pMOS in saturation.
(kn/2) [ 2(VGS,n- V TO,n) VDS,n – V2DS,n] = kp/2 [ (VGS,p- V TO,p)2]
(kn/2) [ 2(V in- V TO,n) Vout–Vout2 ] = (kp/2) [ (V in- VDD-V TO,p) 2
Differentiating both sides with respect to Vin and dVout/dVin = -1
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VIH = (VDD + V TO,p +(2Vout + V TO,n) kR)/1+kR
Where kR = kn/kp
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Vth:
Vth = Vin = Vout
Inverter threshold one of the important parameter.
Both the transistors in saturation.
kn/2 [ (VGS,n- V TO,n)2] = kp/2 [ (VGS,p- V TO,p)2
Substituting
VGS, n = Vin & V GS,p = - ( VDD- Vin)
Vth = (V TO,n + ( 1/kR)1/2 . ( VDD + V TO,p))/ (1+( 1/kR)1/2 )
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Given the Power supply voltage VDD, the nMOS and pMOS transistor threshold
voltage and the inverter switching threshold Vth
The corresponding kR becomes
( 1/kR)1/2 = (Vth -V
TO,n )/(VDD + V TO,p - Vth)
kR = kn/kp = ((VDD + V TO,p - Vth)/ (Vth - V TO,n ))2
V
th, ideal = VDD/2
(kn/kp)ideal = ((0.5VDD + V TO,p )/ (0.5VDD - V TO,n ))2
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For having symmetric input-output characteristics
VTO = V TO,n = V TO,p
kn/kp = 1
n.Cox .( W/L)n/ p.Cox .( W/L)p = n .( W/L)n/ p .( W/L)p
( W/L)n/( W/L)p = n /p = (230 cm2/V-s)/ (580 cm2/V.s)
( W/L)p = 2.5 ( W/L)n
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For a symmetric CMOS inverter with V TO, n = V TO,p and kR = 1
VIL = (1/8) ( 3 VDD + 2V TO,n)
VIH = (1/8) ( 5 VDD - 2V TO,n)
In a symmetric inverter
VIL + VIH = VDD
NML = VIL – VOL = VIL
NMH = VOH – VIH = VDD – VIH = VIL
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Ex: For the CMOS inverter
VT0,N=0.4; VT0,P = -0.4; kn’ = 80A/V2; kp’ = 40 A/V2;
VDD= 3.3V; (W/L)n =2; (W/L)p = 4
(i) Find transition points for n and p MOST
(ii) Find Vin when Vo = 0.4V and Vo = 2.9V
(iii) Repeat above for (W/L)n = (W/L)p = 2
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Switching threshold certain observations:
Vth is relatively insensitive to variations in device ratio. i.e., small
variations of the ratio does not disturb the transfer characteristic that
much.
The effect of changing Wp-Wn ratio is to shift the transient region of the
VTC.
Vth r(VDD)/(1+r)
where r = kp.VDSATp/ kn.VDSATn
Increasing the widths of PMOS or the NMOS moves Vth towards VDD
or GND respectively.
This property is useful as asymmetrical transfer characteristics are
actually desirable in some design.
Ex: to pass an incoming signal with noisy zero value, by raising the
threshold value of the inverter.
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Supply voltage scaling on CMOS inverters:
-CMOS inverter operates over a range of supply voltages.
-Expressions for VIL, VIH, Vth show that static characteristics of
CMOS inverter allow significant variations in supply voltage.
- CMOS inverter will continue to operate correctly with a supply
voltage limit as
VDD min = V TO,n + | V TO, p |
-Correct inverter operation is sustained if at least one of the
transistors remain in conduction.
If power supply voltage is reduced below the sum of the two Threshold
voltages, the VTC will have a region in which none of the transistor is
conducting. Previous output preserved as charge at output node.
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